[PATCH] gianfar: Add support enhanced TSEC features on the MPC 8548
Jeff, Just incase this got lost in the recent netdev mailing list transition here is a nicer version of Andy's patch for gianfar. - kumar * TCP/IP/UDP checksumming and verification * VLAN tag insertion/extraction * Larger multicast hash-table * Padding to align IP headers Also added: * msg lvl support * Some whitespace cleanup Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
This commit is contained in:
Kumar Gala
Jeff Garzik
parent
be83668a25
commit
0bbaf069f0
File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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/*
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/*
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* drivers/net/gianfar.h
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*
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* Gianfar Ethernet Driver
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@ -53,6 +53,12 @@
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/* The maximum number of packets to be handled in one call of gfar_poll */
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#define GFAR_DEV_WEIGHT 64
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/* Length for FCB */
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#define GMAC_FCB_LEN 8
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/* Default padding amount */
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#define DEFAULT_PADDING 2
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/* Number of bytes to align the rx bufs to */
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#define RXBUF_ALIGNMENT 64
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@ -91,7 +97,7 @@ extern const char gfar_driver_version[];
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#define JUMBO_FRAME_SIZE 9600
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/* Latency of interface clock in nanoseconds */
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/* Interface clock latency , in this case, means the
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/* Interface clock latency , in this case, means the
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* time described by a value of 1 in the interrupt
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* coalescing registers' time fields. Since those fields
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* refer to the time it takes for 64 clocks to pass, the
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@ -166,9 +172,28 @@ extern const char gfar_driver_version[];
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mk_ic_icft(count) | \
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mk_ic_ictt(time))
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#define RCTRL_PAL_MASK 0x001f0000
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#define RCTRL_VLEX 0x00002000
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#define RCTRL_FILREN 0x00001000
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#define RCTRL_GHTX 0x00000400
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#define RCTRL_IPCSEN 0x00000200
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#define RCTRL_TUCSEN 0x00000100
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#define RCTRL_PRSDEP_MASK 0x000000c0
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#define RCTRL_PRSDEP_INIT 0x000000c0
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#define RCTRL_PROM 0x00000008
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#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
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| RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
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#define RCTRL_EXTHASH (RCTRL_GHTX)
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#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
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#define RSTAT_CLEAR_RHALT 0x00800000
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#define TCTRL_IPCSEN 0x00004000
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#define TCTRL_TUCSEN 0x00002000
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#define TCTRL_VLINS 0x00001000
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#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
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#define IEVENT_INIT_CLEAR 0xffffffff
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#define IEVENT_BABR 0x80000000
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#define IEVENT_RXC 0x40000000
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@ -187,12 +212,16 @@ extern const char gfar_driver_version[];
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#define IEVENT_RXB0 0x00008000
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#define IEVENT_GRSC 0x00000100
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#define IEVENT_RXF0 0x00000080
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#define IEVENT_FIR 0x00000008
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#define IEVENT_FIQ 0x00000004
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#define IEVENT_DPE 0x00000002
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#define IEVENT_PERR 0x00000001
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#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
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#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
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#define IEVENT_ERR_MASK \
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(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
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IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
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| IEVENT_CRL | IEVENT_XFUN)
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| IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
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#define IMASK_INIT_CLEAR 0x00000000
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#define IMASK_BABR 0x80000000
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@ -212,10 +241,15 @@ extern const char gfar_driver_version[];
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#define IMASK_RXB0 0x00008000
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#define IMASK_GTSC 0x00000100
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#define IMASK_RXFEN0 0x00000080
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#define IMASK_FIR 0x00000008
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#define IMASK_FIQ 0x00000004
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#define IMASK_DPE 0x00000002
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#define IMASK_PERR 0x00000001
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#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
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#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
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IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
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IMASK_XFUN | IMASK_RXC | IMASK_BABT)
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IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
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| IMASK_PERR)
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/* Attribute fields */
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@ -254,6 +288,18 @@ extern const char gfar_driver_version[];
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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#define TXBD_TOE 0x0002
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/* Tx FCB param bits */
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#define TXFCB_VLN 0x80
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#define TXFCB_IP 0x40
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#define TXFCB_IP6 0x20
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#define TXFCB_TUP 0x10
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#define TXFCB_UDP 0x08
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#define TXFCB_CIP 0x04
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#define TXFCB_CTU 0x02
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#define TXFCB_NPH 0x01
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#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
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/* RxBD status field bits */
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#define RXBD_EMPTY 0x8000
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@ -273,6 +319,18 @@ extern const char gfar_driver_version[];
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#define RXBD_TRUNCATED 0x0001
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#define RXBD_STATS 0x01ff
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/* Rx FCB status field bits */
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#define RXFCB_VLN 0x8000
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#define RXFCB_IP 0x4000
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#define RXFCB_IP6 0x2000
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#define RXFCB_TUP 0x1000
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#define RXFCB_CIP 0x0800
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#define RXFCB_CTU 0x0400
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#define RXFCB_EIP 0x0200
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#define RXFCB_ETU 0x0100
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#define RXFCB_PERR_MASK 0x000c
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#define RXFCB_PERR_BADL3 0x0008
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struct txbd8
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{
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u16 status; /* Status Fields */
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@ -280,6 +338,22 @@ struct txbd8
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u32 bufPtr; /* Buffer Pointer */
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};
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struct txfcb {
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u8 vln:1,
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ip:1,
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ip6:1,
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tup:1,
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udp:1,
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cip:1,
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ctu:1,
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nph:1;
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u8 reserved;
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u8 l4os; /* Level 4 Header Offset */
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u8 l3os; /* Level 3 Header Offset */
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u16 phcs; /* Pseudo-header Checksum */
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u16 vlctl; /* VLAN control word */
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};
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struct rxbd8
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{
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u16 status; /* Status Fields */
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@ -287,6 +361,21 @@ struct rxbd8
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u32 bufPtr; /* Buffer Pointer */
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};
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struct rxfcb {
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u16 vln:1,
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ip:1,
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ip6:1,
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tup:1,
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cip:1,
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ctu:1,
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eip:1,
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etu:1;
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u8 rq; /* Receive Queue index */
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u8 pro; /* Layer 4 Protocol */
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u16 reserved;
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u16 vlctl; /* VLAN control word */
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};
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struct rmon_mib
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{
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u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
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@ -371,90 +460,191 @@ struct gfar_stats {
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struct gfar {
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u8 res1[16];
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u32 ievent; /* 0x.010 - Interrupt Event Register */
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u32 imask; /* 0x.014 - Interrupt Mask Register */
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u32 edis; /* 0x.018 - Error Disabled Register */
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u32 tsec_id; /* 0x.000 - Controller ID register */
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u8 res1[12];
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u32 ievent; /* 0x.010 - Interrupt Event Register */
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u32 imask; /* 0x.014 - Interrupt Mask Register */
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u32 edis; /* 0x.018 - Error Disabled Register */
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u8 res2[4];
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u32 ecntrl; /* 0x.020 - Ethernet Control Register */
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u32 minflr; /* 0x.024 - Minimum Frame Length Register */
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u32 ptv; /* 0x.028 - Pause Time Value Register */
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u32 dmactrl; /* 0x.02c - DMA Control Register */
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u32 tbipa; /* 0x.030 - TBI PHY Address Register */
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u32 ecntrl; /* 0x.020 - Ethernet Control Register */
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u32 minflr; /* 0x.024 - Minimum Frame Length Register */
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u32 ptv; /* 0x.028 - Pause Time Value Register */
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u32 dmactrl; /* 0x.02c - DMA Control Register */
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u32 tbipa; /* 0x.030 - TBI PHY Address Register */
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u8 res3[88];
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u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
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u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
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u8 res4[8];
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u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
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u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
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u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
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u8 res5[96];
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u32 tctrl; /* 0x.100 - Transmit Control Register */
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u32 tstat; /* 0x.104 - Transmit Status Register */
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u8 res6[4];
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u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
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u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
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u8 res7[16];
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u32 ctbptr; /* 0x.124 - Current Transmit Buffer Descriptor Pointer Register */
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u8 res8[92];
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u32 tbptr; /* 0x.184 - Transmit Buffer Descriptor Pointer Low Register */
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u8 res9[124];
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u32 tbase; /* 0x.204 - Transmit Descriptor Base Address Register */
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u8 res10[168];
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u32 ostbd; /* 0x.2b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
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u32 ostbdp; /* 0x.2b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
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u8 res11[72];
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u32 rctrl; /* 0x.300 - Receive Control Register */
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u32 rstat; /* 0x.304 - Receive Status Register */
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u8 res12[4];
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u32 rbdlen; /* 0x.30c - RxBD Data Length Register */
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u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
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u8 res13[16];
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u32 crbptr; /* 0x.324 - Current Receive Buffer Descriptor Pointer */
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u8 res14[24];
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u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
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u8 res15[64];
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u32 rbptr; /* 0x.384 - Receive Buffer Descriptor Pointer */
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u8 res16[124];
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u32 rbase; /* 0x.404 - Receive Descriptor Base Address */
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u8 res17[248];
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u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
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u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
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u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
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u32 hafdup; /* 0x.50c - Half Duplex Register */
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u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
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u8 res5[4];
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u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
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u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
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u8 res6[84];
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u32 tctrl; /* 0x.100 - Transmit Control Register */
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u32 tstat; /* 0x.104 - Transmit Status Register */
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u32 dfvlan; /* 0x.108 - Default VLAN Control word */
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u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
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u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
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u32 tqueue; /* 0x.114 - Transmit queue control register */
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u8 res7[40];
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u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
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u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
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u8 res8[52];
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u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
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u8 res9a[4];
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u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
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u8 res9b[4];
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u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
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u8 res9c[4];
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u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
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u8 res9d[4];
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u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
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u8 res9e[4];
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u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
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u8 res9f[4];
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u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
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u8 res9g[4];
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u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
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u8 res9h[4];
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u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
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u8 res9[64];
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u32 tbaseh; /* 0x.200 - TxBD base address high */
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u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
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u8 res10a[4];
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u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
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u8 res10b[4];
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u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
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u8 res10c[4];
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u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
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u8 res10d[4];
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u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
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u8 res10e[4];
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u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
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u8 res10f[4];
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u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
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u8 res10g[4];
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u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
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u8 res10[192];
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u32 rctrl; /* 0x.300 - Receive Control Register */
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u32 rstat; /* 0x.304 - Receive Status Register */
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u8 res12[8];
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u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
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u32 rqueue; /* 0x.314 - Receive queue control register */
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u8 res13[24];
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u32 rbifx; /* 0x.330 - Receive bit field extract control register */
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u32 rqfar; /* 0x.334 - Receive queue filing table address register */
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u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
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u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
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u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
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u8 res14[56];
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u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
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u8 res15a[4];
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u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
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u8 res15b[4];
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u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
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u8 res15c[4];
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u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
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u8 res15d[4];
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u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
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u8 res15e[4];
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u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
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u8 res15f[4];
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u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
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u8 res15g[4];
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u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
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u8 res15h[4];
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u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
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u8 res16[64];
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u32 rbaseh; /* 0x.400 - RxBD base address high */
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u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
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u8 res17a[4];
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u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
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u8 res17b[4];
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u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
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u8 res17c[4];
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u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
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u8 res17d[4];
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u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
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u8 res17e[4];
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u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
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u8 res17f[4];
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u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
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u8 res17g[4];
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u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
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u8 res17[192];
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u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
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u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
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u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
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u32 hafdup; /* 0x.50c - Half Duplex Register */
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u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
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u8 res18[12];
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u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
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u32 miimcom; /* 0x.524 - MII Management Command Register */
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u32 miimadd; /* 0x.528 - MII Management Address Register */
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u32 miimcon; /* 0x.52c - MII Management Control Register */
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u32 miimstat; /* 0x.530 - MII Management Status Register */
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u32 miimind; /* 0x.534 - MII Management Indicator Register */
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u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
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u32 miimcom; /* 0x.524 - MII Management Command Register */
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u32 miimadd; /* 0x.528 - MII Management Address Register */
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u32 miimcon; /* 0x.52c - MII Management Control Register */
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u32 miimstat; /* 0x.530 - MII Management Status Register */
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u32 miimind; /* 0x.534 - MII Management Indicator Register */
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u8 res19[4];
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u32 ifstat; /* 0x.53c - Interface Status Register */
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u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
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u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
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u8 res20[312];
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struct rmon_mib rmon;
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u8 res21[192];
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u32 iaddr0; /* 0x.800 - Indivdual address register 0 */
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u32 iaddr1; /* 0x.804 - Indivdual address register 1 */
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u32 iaddr2; /* 0x.808 - Indivdual address register 2 */
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u32 iaddr3; /* 0x.80c - Indivdual address register 3 */
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u32 iaddr4; /* 0x.810 - Indivdual address register 4 */
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u32 iaddr5; /* 0x.814 - Indivdual address register 5 */
|
||||
u32 iaddr6; /* 0x.818 - Indivdual address register 6 */
|
||||
u32 iaddr7; /* 0x.81c - Indivdual address register 7 */
|
||||
u32 ifstat; /* 0x.53c - Interface Status Register */
|
||||
u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
|
||||
u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
|
||||
u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
|
||||
u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
|
||||
u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
|
||||
u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
|
||||
u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
|
||||
u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
|
||||
u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
|
||||
u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
|
||||
u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
|
||||
u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
|
||||
u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
|
||||
u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
|
||||
u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
|
||||
u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
|
||||
u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
|
||||
u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
|
||||
u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
|
||||
u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
|
||||
u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
|
||||
u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
|
||||
u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
|
||||
u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
|
||||
u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
|
||||
u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
|
||||
u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
|
||||
u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
|
||||
u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
|
||||
u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
|
||||
u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
|
||||
u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
|
||||
u8 res20[192];
|
||||
struct rmon_mib rmon; /* 0x.680-0x.73c */
|
||||
u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
|
||||
u8 res21[188];
|
||||
u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
|
||||
u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
|
||||
u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
|
||||
u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
|
||||
u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
|
||||
u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
|
||||
u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
|
||||
u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
|
||||
u8 res22[96];
|
||||
u32 gaddr0; /* 0x.880 - Global address register 0 */
|
||||
u32 gaddr1; /* 0x.884 - Global address register 1 */
|
||||
u32 gaddr2; /* 0x.888 - Global address register 2 */
|
||||
u32 gaddr3; /* 0x.88c - Global address register 3 */
|
||||
u32 gaddr4; /* 0x.890 - Global address register 4 */
|
||||
u32 gaddr5; /* 0x.894 - Global address register 5 */
|
||||
u32 gaddr6; /* 0x.898 - Global address register 6 */
|
||||
u32 gaddr7; /* 0x.89c - Global address register 7 */
|
||||
u8 res23[856];
|
||||
u32 attr; /* 0x.bf8 - Attributes Register */
|
||||
u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
|
||||
u32 gaddr0; /* 0x.880 - Group address register 0 */
|
||||
u32 gaddr1; /* 0x.884 - Group address register 1 */
|
||||
u32 gaddr2; /* 0x.888 - Group address register 2 */
|
||||
u32 gaddr3; /* 0x.88c - Group address register 3 */
|
||||
u32 gaddr4; /* 0x.890 - Group address register 4 */
|
||||
u32 gaddr5; /* 0x.894 - Group address register 5 */
|
||||
u32 gaddr6; /* 0x.898 - Group address register 6 */
|
||||
u32 gaddr7; /* 0x.89c - Group address register 7 */
|
||||
u8 res23a[352];
|
||||
u32 fifocfg; /* 0x.a00 - FIFO interface config register */
|
||||
u8 res23b[252];
|
||||
u8 res23c[248];
|
||||
u32 attr; /* 0x.bf8 - Attributes Register */
|
||||
u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
|
||||
u8 res24[1024];
|
||||
|
||||
};
|
||||
|
|
@ -496,6 +686,8 @@ struct gfar_private {
|
|||
struct txbd8 *cur_tx; /* Next free ring entry */
|
||||
struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
|
||||
struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
|
||||
u32 *hash_regs[16];
|
||||
int hash_width;
|
||||
struct gfar *phyregs;
|
||||
struct work_struct tq;
|
||||
struct timer_list phy_info_timer;
|
||||
|
|
@ -506,9 +698,12 @@ struct gfar_private {
|
|||
unsigned int rx_stash_size;
|
||||
unsigned int tx_ring_size;
|
||||
unsigned int rx_ring_size;
|
||||
wait_queue_head_t rxcleanupq;
|
||||
unsigned int rxclean;
|
||||
|
||||
unsigned char vlan_enable:1,
|
||||
rx_csum_enable:1,
|
||||
extended_hash:1;
|
||||
unsigned short padding;
|
||||
struct vlan_group *vlgrp;
|
||||
/* Info structure initialized by board setup code */
|
||||
unsigned int interruptTransmit;
|
||||
unsigned int interruptReceive;
|
||||
|
|
@ -519,6 +714,8 @@ struct gfar_private {
|
|||
int oldspeed;
|
||||
int oldduplex;
|
||||
int oldlink;
|
||||
|
||||
uint32_t msg_enable;
|
||||
};
|
||||
|
||||
extern inline u32 gfar_read(volatile unsigned *addr)
|
||||
|
|
|
|||
|
|
@ -46,16 +46,18 @@
|
|||
|
||||
extern int startup_gfar(struct net_device *dev);
|
||||
extern void stop_gfar(struct net_device *dev);
|
||||
extern void gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
|
||||
extern void gfar_halt(struct net_device *dev);
|
||||
extern void gfar_start(struct net_device *dev);
|
||||
extern int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
|
||||
|
||||
void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
|
||||
static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
|
||||
u64 * buf);
|
||||
void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf);
|
||||
int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
|
||||
int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
|
||||
void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
|
||||
int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
|
||||
void gfar_gdrvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo);
|
||||
static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf);
|
||||
static int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
|
||||
static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals);
|
||||
static void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
|
||||
static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals);
|
||||
static void gfar_gdrvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo);
|
||||
|
||||
static char stat_gstrings[][ETH_GSTRING_LEN] = {
|
||||
"rx-dropped-by-kernel",
|
||||
|
|
@ -118,57 +120,56 @@ static char stat_gstrings[][ETH_GSTRING_LEN] = {
|
|||
"tx-fragmented-frames",
|
||||
};
|
||||
|
||||
/* Fill in a buffer with the strings which correspond to the
|
||||
* stats */
|
||||
static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
|
||||
memcpy(buf, stat_gstrings, GFAR_STATS_LEN * ETH_GSTRING_LEN);
|
||||
else
|
||||
memcpy(buf, stat_gstrings,
|
||||
GFAR_EXTRA_STATS_LEN * ETH_GSTRING_LEN);
|
||||
}
|
||||
|
||||
/* Fill in an array of 64-bit statistics from various sources.
|
||||
* This array will be appended to the end of the ethtool_stats
|
||||
* structure, and returned to user space
|
||||
*/
|
||||
void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf)
|
||||
static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, u64 * buf)
|
||||
{
|
||||
int i;
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
u32 *rmon = (u32 *) & priv->regs->rmon;
|
||||
u64 *extra = (u64 *) & priv->extra_stats;
|
||||
struct gfar_stats *stats = (struct gfar_stats *) buf;
|
||||
|
||||
for (i = 0; i < GFAR_RMON_LEN; i++) {
|
||||
stats->rmon[i] = (u64) (rmon[i]);
|
||||
}
|
||||
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
|
||||
u32 *rmon = (u32 *) & priv->regs->rmon;
|
||||
struct gfar_stats *stats = (struct gfar_stats *) buf;
|
||||
|
||||
for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++) {
|
||||
stats->extra[i] = extra[i];
|
||||
}
|
||||
for (i = 0; i < GFAR_RMON_LEN; i++)
|
||||
stats->rmon[i] = (u64) (rmon[i]);
|
||||
|
||||
for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
|
||||
stats->extra[i] = extra[i];
|
||||
} else
|
||||
for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
|
||||
buf[i] = extra[i];
|
||||
}
|
||||
|
||||
/* Returns the number of stats (and their corresponding strings) */
|
||||
int gfar_stats_count(struct net_device *dev)
|
||||
static int gfar_stats_count(struct net_device *dev)
|
||||
{
|
||||
return GFAR_STATS_LEN;
|
||||
}
|
||||
|
||||
void gfar_gstrings_normon(struct net_device *dev, u32 stringset, u8 * buf)
|
||||
{
|
||||
memcpy(buf, stat_gstrings, GFAR_EXTRA_STATS_LEN * ETH_GSTRING_LEN);
|
||||
}
|
||||
|
||||
void gfar_fill_stats_normon(struct net_device *dev,
|
||||
struct ethtool_stats *dummy, u64 * buf)
|
||||
{
|
||||
int i;
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
u64 *extra = (u64 *) & priv->extra_stats;
|
||||
|
||||
for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++) {
|
||||
buf[i] = extra[i];
|
||||
}
|
||||
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
|
||||
return GFAR_STATS_LEN;
|
||||
else
|
||||
return GFAR_EXTRA_STATS_LEN;
|
||||
}
|
||||
|
||||
|
||||
int gfar_stats_count_normon(struct net_device *dev)
|
||||
{
|
||||
return GFAR_EXTRA_STATS_LEN;
|
||||
}
|
||||
/* Fills in the drvinfo structure with some basic info */
|
||||
void gfar_gdrvinfo(struct net_device *dev, struct
|
||||
static void gfar_gdrvinfo(struct net_device *dev, struct
|
||||
ethtool_drvinfo *drvinfo)
|
||||
{
|
||||
strncpy(drvinfo->driver, DRV_NAME, GFAR_INFOSTR_LEN);
|
||||
|
|
@ -182,7 +183,7 @@ void gfar_gdrvinfo(struct net_device *dev, struct
|
|||
}
|
||||
|
||||
/* Return the current settings in the ethtool_cmd structure */
|
||||
int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||
static int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
uint gigabit_support =
|
||||
|
|
@ -216,13 +217,13 @@ int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|||
}
|
||||
|
||||
/* Return the length of the register structure */
|
||||
int gfar_reglen(struct net_device *dev)
|
||||
static int gfar_reglen(struct net_device *dev)
|
||||
{
|
||||
return sizeof (struct gfar);
|
||||
}
|
||||
|
||||
/* Return a dump of the GFAR register space */
|
||||
void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
|
||||
static void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
|
||||
{
|
||||
int i;
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
|
@ -233,13 +234,6 @@ void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regb
|
|||
buf[i] = theregs[i];
|
||||
}
|
||||
|
||||
/* Fill in a buffer with the strings which correspond to the
|
||||
* stats */
|
||||
void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
|
||||
{
|
||||
memcpy(buf, stat_gstrings, GFAR_STATS_LEN * ETH_GSTRING_LEN);
|
||||
}
|
||||
|
||||
/* Convert microseconds to ethernet clock ticks, which changes
|
||||
* depending on what speed the controller is running at */
|
||||
static unsigned int gfar_usecs2ticks(struct gfar_private *priv, unsigned int usecs)
|
||||
|
|
@ -291,9 +285,12 @@ static unsigned int gfar_ticks2usecs(struct gfar_private *priv, unsigned int tic
|
|||
|
||||
/* Get the coalescing parameters, and put them in the cvals
|
||||
* structure. */
|
||||
int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
||||
static int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
cvals->rx_coalesce_usecs = gfar_ticks2usecs(priv, priv->rxtime);
|
||||
cvals->rx_max_coalesced_frames = priv->rxcount;
|
||||
|
|
@ -337,10 +334,13 @@ int gfar_gcoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
|||
* Both cvals->*_usecs and cvals->*_frames have to be > 0
|
||||
* in order for coalescing to be active
|
||||
*/
|
||||
int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
||||
static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* Set up rx coalescing */
|
||||
if ((cvals->rx_coalesce_usecs == 0) ||
|
||||
(cvals->rx_max_coalesced_frames == 0))
|
||||
|
|
@ -379,7 +379,7 @@ int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals)
|
|||
/* Fills in rvals with the current ring parameters. Currently,
|
||||
* rx, rx_mini, and rx_jumbo rings are the same size, as mini and
|
||||
* jumbo are ignored by the driver */
|
||||
void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
||||
static void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
|
|
@ -401,9 +401,8 @@ void gfar_gringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
|||
* necessary so that we don't mess things up while we're in
|
||||
* motion. We wait for the ring to be clean before reallocating
|
||||
* the rings. */
|
||||
int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
||||
static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
||||
{
|
||||
u32 tempval;
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
int err = 0;
|
||||
|
||||
|
|
@ -425,44 +424,116 @@ int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rvals)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Stop the controller so we don't rx any more frames */
|
||||
/* But first, make sure we clear the bits */
|
||||
tempval = gfar_read(&priv->regs->dmactrl);
|
||||
tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
|
||||
gfar_write(&priv->regs->dmactrl, tempval);
|
||||
|
||||
tempval = gfar_read(&priv->regs->dmactrl);
|
||||
tempval |= (DMACTRL_GRS | DMACTRL_GTS);
|
||||
gfar_write(&priv->regs->dmactrl, tempval);
|
||||
|
||||
while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
|
||||
cpu_relax();
|
||||
|
||||
/* Note that rx is not clean right now */
|
||||
priv->rxclean = 0;
|
||||
|
||||
if (dev->flags & IFF_UP) {
|
||||
/* Tell the driver to process the rest of the frames */
|
||||
gfar_receive(0, (void *) dev, NULL);
|
||||
unsigned long flags;
|
||||
|
||||
/* Now wait for it to be done */
|
||||
wait_event_interruptible(priv->rxcleanupq, priv->rxclean);
|
||||
|
||||
/* Ok, all packets have been handled. Now we bring it down,
|
||||
* change the ring size, and bring it up */
|
||||
/* Halt TX and RX, and process the frames which
|
||||
* have already been received */
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
gfar_halt(dev);
|
||||
gfar_clean_rx_ring(dev, priv->rx_ring_size);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
/* Now we take down the rings to rebuild them */
|
||||
stop_gfar(dev);
|
||||
}
|
||||
|
||||
/* Change the size */
|
||||
priv->rx_ring_size = rvals->rx_pending;
|
||||
priv->tx_ring_size = rvals->tx_pending;
|
||||
|
||||
/* Rebuild the rings with the new size */
|
||||
if (dev->flags & IFF_UP)
|
||||
err = startup_gfar(dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
int err = 0;
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (dev->flags & IFF_UP) {
|
||||
unsigned long flags;
|
||||
|
||||
/* Halt TX and RX, and process the frames which
|
||||
* have already been received */
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
gfar_halt(dev);
|
||||
gfar_clean_rx_ring(dev, priv->rx_ring_size);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
/* Now we take down the rings to rebuild them */
|
||||
stop_gfar(dev);
|
||||
}
|
||||
|
||||
priv->rx_csum_enable = data;
|
||||
|
||||
if (dev->flags & IFF_UP)
|
||||
err = startup_gfar(dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static uint32_t gfar_get_rx_csum(struct net_device *dev)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
|
||||
return 0;
|
||||
|
||||
return priv->rx_csum_enable;
|
||||
}
|
||||
|
||||
static int gfar_set_tx_csum(struct net_device *dev, uint32_t data)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
gfar_halt(dev);
|
||||
|
||||
if (data)
|
||||
dev->features |= NETIF_F_IP_CSUM;
|
||||
else
|
||||
dev->features &= ~NETIF_F_IP_CSUM;
|
||||
|
||||
gfar_start(dev);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t gfar_get_tx_csum(struct net_device *dev)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
|
||||
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
|
||||
return 0;
|
||||
|
||||
return (dev->features & NETIF_F_IP_CSUM) != 0;
|
||||
}
|
||||
|
||||
static uint32_t gfar_get_msglevel(struct net_device *dev)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
return priv->msg_enable;
|
||||
}
|
||||
|
||||
static void gfar_set_msglevel(struct net_device *dev, uint32_t data)
|
||||
{
|
||||
struct gfar_private *priv = netdev_priv(dev);
|
||||
priv->msg_enable = data;
|
||||
}
|
||||
|
||||
|
||||
struct ethtool_ops gfar_ethtool_ops = {
|
||||
.get_settings = gfar_gsettings,
|
||||
.get_drvinfo = gfar_gdrvinfo,
|
||||
|
|
@ -476,52 +547,10 @@ struct ethtool_ops gfar_ethtool_ops = {
|
|||
.get_strings = gfar_gstrings,
|
||||
.get_stats_count = gfar_stats_count,
|
||||
.get_ethtool_stats = gfar_fill_stats,
|
||||
};
|
||||
|
||||
struct ethtool_ops gfar_normon_nocoalesce_ethtool_ops = {
|
||||
.get_settings = gfar_gsettings,
|
||||
.get_drvinfo = gfar_gdrvinfo,
|
||||
.get_regs_len = gfar_reglen,
|
||||
.get_regs = gfar_get_regs,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_ringparam = gfar_gringparam,
|
||||
.set_ringparam = gfar_sringparam,
|
||||
.get_strings = gfar_gstrings_normon,
|
||||
.get_stats_count = gfar_stats_count_normon,
|
||||
.get_ethtool_stats = gfar_fill_stats_normon,
|
||||
};
|
||||
|
||||
struct ethtool_ops gfar_nocoalesce_ethtool_ops = {
|
||||
.get_settings = gfar_gsettings,
|
||||
.get_drvinfo = gfar_gdrvinfo,
|
||||
.get_regs_len = gfar_reglen,
|
||||
.get_regs = gfar_get_regs,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_ringparam = gfar_gringparam,
|
||||
.set_ringparam = gfar_sringparam,
|
||||
.get_strings = gfar_gstrings,
|
||||
.get_stats_count = gfar_stats_count,
|
||||
.get_ethtool_stats = gfar_fill_stats,
|
||||
};
|
||||
|
||||
struct ethtool_ops gfar_normon_ethtool_ops = {
|
||||
.get_settings = gfar_gsettings,
|
||||
.get_drvinfo = gfar_gdrvinfo,
|
||||
.get_regs_len = gfar_reglen,
|
||||
.get_regs = gfar_get_regs,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_coalesce = gfar_gcoalesce,
|
||||
.set_coalesce = gfar_scoalesce,
|
||||
.get_ringparam = gfar_gringparam,
|
||||
.set_ringparam = gfar_sringparam,
|
||||
.get_strings = gfar_gstrings_normon,
|
||||
.get_stats_count = gfar_stats_count_normon,
|
||||
.get_ethtool_stats = gfar_fill_stats_normon,
|
||||
};
|
||||
|
||||
struct ethtool_ops *gfar_op_array[] = {
|
||||
&gfar_ethtool_ops,
|
||||
&gfar_normon_ethtool_ops,
|
||||
&gfar_nocoalesce_ethtool_ops,
|
||||
&gfar_normon_nocoalesce_ethtool_ops
|
||||
.get_rx_csum = gfar_get_rx_csum,
|
||||
.get_tx_csum = gfar_get_tx_csum,
|
||||
.set_rx_csum = gfar_set_rx_csum,
|
||||
.set_tx_csum = gfar_set_tx_csum,
|
||||
.get_msglevel = gfar_get_msglevel,
|
||||
.set_msglevel = gfar_set_msglevel,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue