ARM: perf: use cpumask_t to record active IRQs
Commit 5dfc54e0
("ARM: GIC: avoid routing interrupts to offline CPUs")
prevents the GIC from setting the affinity of an IRQ to a CPU with
id >= nr_cpu_ids. This was previously abused by perf on some platforms
where more IRQs were registered than possible CPUs.
This patch fixes the problem by using a cpumask_t to keep track of the
active (requested) interrupts in perf. The same effect could be achieved
by limiting the number of IRQs to the number of CPUs, but using a mask
instead will be useful for adding extended CPU hotplug support in the
future.
Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
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@ -69,6 +69,7 @@ static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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struct arm_pmu {
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enum arm_perf_pmu_ids id;
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cpumask_t active_irqs;
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const char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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@ -388,6 +389,25 @@ static irqreturn_t armpmu_platform_irq(int irq, void *dev)
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return plat->handle_irq(irq, dev, armpmu->handle_irq);
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}
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static void
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armpmu_release_hardware(void)
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{
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int i, irq, irqs;
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irqs = min(pmu_device->num_resources, num_possible_cpus());
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for (i = 0; i < irqs; ++i) {
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if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
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continue;
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, NULL);
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}
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armpmu->stop();
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release_pmu(ARM_PMU_DEVICE_CPU);
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}
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static int
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armpmu_reserve_hardware(void)
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{
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@ -401,20 +421,20 @@ armpmu_reserve_hardware(void)
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return err;
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}
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irqs = pmu_device->num_resources;
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plat = dev_get_platdata(&pmu_device->dev);
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if (plat && plat->handle_irq)
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handle_irq = armpmu_platform_irq;
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else
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handle_irq = armpmu->handle_irq;
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irqs = min(pmu_device->num_resources, num_possible_cpus());
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if (irqs < 1) {
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pr_err("no irqs for PMUs defined\n");
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return -ENODEV;
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}
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for (i = 0; i < irqs; ++i) {
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err = 0;
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irq = platform_get_irq(pmu_device, i);
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if (irq < 0)
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continue;
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@ -422,13 +442,12 @@ armpmu_reserve_hardware(void)
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/*
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* If we have a single PMU interrupt that we can't shift,
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* assume that we're running on a uniprocessor machine and
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* continue.
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* continue. Otherwise, continue without this interrupt.
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*/
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err = irq_set_affinity(irq, cpumask_of(i));
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if (err && irqs > 1) {
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pr_err("unable to set irq affinity (irq=%d, cpu=%u)\n",
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irq, i);
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break;
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if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
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pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
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irq, i);
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continue;
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}
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err = request_irq(irq, handle_irq,
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@ -437,35 +456,14 @@ armpmu_reserve_hardware(void)
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if (err) {
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pr_err("unable to request IRQ%d for ARM PMU counters\n",
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irq);
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break;
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armpmu_release_hardware();
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return err;
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}
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cpumask_set_cpu(i, &armpmu->active_irqs);
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}
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if (err) {
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for (i = i - 1; i >= 0; --i) {
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, NULL);
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}
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release_pmu(ARM_PMU_DEVICE_CPU);
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}
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return err;
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}
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static void
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armpmu_release_hardware(void)
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{
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int i, irq;
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for (i = pmu_device->num_resources - 1; i >= 0; --i) {
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, NULL);
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}
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armpmu->stop();
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release_pmu(ARM_PMU_DEVICE_CPU);
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return 0;
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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