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RISC-V: alternatives: Support patching multiple insns in assembly 

As pointed out in commit d374a16539 ("RISC-V: fix compile error
from deduplicated __ALTERNATIVE_CFG_2"), we need quotes around
parameters passed to macros within macros to avoid spaces being
interpreted as separators. ALT_NEW_CONTENT was trying to handle
this by defining new_c has a vararg, but this isn't sufficient
for calling ALTERNATIVE() from assembly with multiple instructions
in the new/old sequences. Remove the vararg "hack" and use quotes.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230224162631.405473-2-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Andrew Jones 2023-02-24 17:26:24 +01:00 committed by Palmer Dabbelt
parent 816a697441
commit 0b2f658f53
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 3 additions and 3 deletions
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6
arch/riscv/include/asm/alternative-macros.h
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@ -14,7 +14,7 @@
.4byte \patch_id
.endm
.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c : vararg
.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c
.if \enable
.pushsection .alternative, "a"
ALT_ENTRY 886b, 888f, \vendor_id, \patch_id, 889f - 888f
@ -41,13 +41,13 @@
\old_c
.option pop
887 :
ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, \new_c
ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, "\new_c"
.endm
.macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, patch_id_1, enable_1, \
new_c_2, vendor_id_2, patch_id_2, enable_2
ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \patch_id_1, \enable_1
ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, \new_c_2
ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2"
.endm
#define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__