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drm/amdgpu/psp: avoid hard-code fence value pre submission 

Hard-code submission fence is not a sustainable way as there is
more and more run-time psp kernel mode submission from driver to
fw

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2018-09-28 14:23:11 +08:00 committed by Alex Deucher
parent 7cd52c917a
commit 0b25cbf9c2
2 changed files with 16 additions and 9 deletions
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20
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -118,22 +118,26 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
static int static int
psp_cmd_submit_buf(struct psp_context *psp, psp_cmd_submit_buf(struct psp_context *psp,
struct amdgpu_firmware_info *ucode, struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr, struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
int index)
{ {
int ret; int ret;
int index;
memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
index = atomic_inc_return(&psp->fence_value);
ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr, ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
fence_mc_addr, index); fence_mc_addr, index);
if (ret) {
while (*((unsigned int *)psp->fence_buf) != index) { atomic_dec(&psp->fence_value);
msleep(1); return ret;
} }
while (*((unsigned int *)psp->fence_buf) != index)
msleep(1);
/* the status field must be 0 after FW is loaded */ /* the status field must be 0 after FW is loaded */
if (ucode && psp->cmd_buf_mem->resp.status) { if (ucode && psp->cmd_buf_mem->resp.status) {
DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n", DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
@ -191,7 +195,7 @@ static int psp_tmr_load(struct psp_context *psp)
PSP_TMR_SIZE, psp->tmr_mc_addr); PSP_TMR_SIZE, psp->tmr_mc_addr);
ret = psp_cmd_submit_buf(psp, NULL, cmd, ret = psp_cmd_submit_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr, 1); psp->fence_buf_mc_addr);
if (ret) if (ret)
goto failed; goto failed;
@ -258,7 +262,7 @@ static int psp_asd_load(struct psp_context *psp)
psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE); psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
ret = psp_cmd_submit_buf(psp, NULL, cmd, ret = psp_cmd_submit_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr, 2); psp->fence_buf_mc_addr);
kfree(cmd); kfree(cmd);
@ -321,7 +325,7 @@ static int psp_np_fw_load(struct psp_context *psp)
return ret; return ret;
ret = psp_cmd_submit_buf(psp, ucode, psp->cmd, ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
psp->fence_buf_mc_addr, i + 3); psp->fence_buf_mc_addr);
if (ret) if (ret)
return ret; return ret;

5
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View File

@ -96,7 +96,7 @@ struct psp_context
const struct psp_funcs *funcs; const struct psp_funcs *funcs;
/* fence buffer */ /* firmware buffer */
struct amdgpu_bo *fw_pri_bo; struct amdgpu_bo *fw_pri_bo;
uint64_t fw_pri_mc_addr; uint64_t fw_pri_mc_addr;
void *fw_pri_buf; void *fw_pri_buf;
@ -134,6 +134,9 @@ struct psp_context
struct amdgpu_bo *cmd_buf_bo; struct amdgpu_bo *cmd_buf_bo;
uint64_t cmd_buf_mc_addr; uint64_t cmd_buf_mc_addr;
struct psp_gfx_cmd_resp *cmd_buf_mem; struct psp_gfx_cmd_resp *cmd_buf_mem;
/* fence value associated with cmd buffer */
atomic_t fence_value;
}; };
struct amdgpu_psp_funcs { struct amdgpu_psp_funcs {