clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Jonathan Marek
Stephen Boyd
parent
c8b9002f44
commit
0b01489475
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@ -101,21 +101,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_FRAC] = 0x38,
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},
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[CLK_ALPHA_PLL_TYPE_TRION] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_CAL_L_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_USER_CTL_U1] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1c,
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[PLL_OFF_CONFIG_CTL_U1] = 0x20,
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[PLL_OFF_TEST_CTL] = 0x24,
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[PLL_OFF_TEST_CTL_U] = 0x28,
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[PLL_OFF_STATUS] = 0x30,
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[PLL_OFF_OPMODE] = 0x38,
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[PLL_OFF_ALPHA_VAL] = 0x40,
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},
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[CLK_ALPHA_PLL_TYPE_LUCID] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_CAL_L_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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@ -154,9 +139,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define PLL_OUT_MASK 0x7
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#define PLL_RATE_MARGIN 500
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/* LUCID PLL specific settings and offsets */
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#define LUCID_PLL_CAL_VAL 0x44
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#define LUCID_PCAL_DONE BIT(26)
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/* TRION PLL specific settings and offsets */
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#define TRION_PLL_CAL_VAL 0x44
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#define TRION_PCAL_DONE BIT(26)
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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@ -910,14 +895,14 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
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const struct clk_ops clk_trion_fixed_pll_ops = {
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const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
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.enable = clk_trion_pll_enable,
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.disable = clk_trion_pll_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
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static unsigned long
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clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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@ -1337,12 +1322,12 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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val << PLL_POST_DIV_SHIFT);
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}
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const struct clk_ops clk_trion_pll_postdiv_ops = {
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const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
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.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
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.round_rate = clk_trion_pll_postdiv_round_rate,
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.set_rate = clk_trion_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
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static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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@ -1397,13 +1382,13 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
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* @regmap: register map
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* @config: configuration to apply for pll
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*/
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void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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if (config->l)
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regmap_write(regmap, PLL_L_VAL(pll), config->l);
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regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
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regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
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if (config->alpha)
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regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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@ -1456,13 +1441,13 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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/* Place the PLL in STANDBY mode */
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
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EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
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/*
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* The Lucid PLL requires a power-on self-calibration which happens when the
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* The TRION PLL requires a power-on self-calibration which happens when the
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* PLL comes out of reset. Calibrate in case it is not completed.
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*/
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static int alpha_pll_lucid_prepare(struct clk_hw *hw)
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static int alpha_pll_trion_prepare(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 regval;
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@ -1470,7 +1455,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
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/* Return early if calibration is not needed. */
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regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val);
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if (regval & LUCID_PCAL_DONE)
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if (regval & TRION_PCAL_DONE)
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return 0;
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/* On/off to calibrate */
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@ -1481,7 +1466,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
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return ret;
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}
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static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
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static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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@ -1535,26 +1520,17 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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}
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const struct clk_ops clk_alpha_pll_lucid_ops = {
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.prepare = alpha_pll_lucid_prepare,
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const struct clk_ops clk_alpha_pll_trion_ops = {
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.prepare = alpha_pll_trion_prepare,
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.enable = clk_trion_pll_enable,
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.disable = clk_trion_pll_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = alpha_pll_lucid_set_rate,
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.set_rate = alpha_pll_trion_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
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const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
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.enable = clk_trion_pll_enable,
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.disable = clk_trion_pll_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
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const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
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.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
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@ -14,7 +14,7 @@ enum {
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CLK_ALPHA_PLL_TYPE_BRAMMO,
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CLK_ALPHA_PLL_TYPE_FABIA,
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CLK_ALPHA_PLL_TYPE_TRION,
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CLK_ALPHA_PLL_TYPE_LUCID,
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CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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@ -134,18 +134,23 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_lucid_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
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extern const struct clk_ops clk_alpha_pll_trion_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
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#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops
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#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
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extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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#define clk_lucid_pll_configure(pll, regmap, config) \
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clk_trion_pll_configure(pll, regmap, config)
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extern const struct clk_ops clk_trion_fixed_pll_ops;
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extern const struct clk_ops clk_trion_pll_postdiv_ops;
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#endif
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@ -53,7 +53,7 @@ static struct clk_alpha_pll gpll0 = {
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.name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_trion_fixed_pll_ops,
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.ops = &clk_alpha_pll_fixed_trion_ops,
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},
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},
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};
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@ -79,7 +79,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
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.hw = &gpll0.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_trion_pll_postdiv_ops,
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.ops = &clk_alpha_pll_postdiv_trion_ops,
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},
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};
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@ -98,7 +98,7 @@ static struct clk_alpha_pll gpll7 = {
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.name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_trion_fixed_pll_ops,
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.ops = &clk_alpha_pll_fixed_trion_ops,
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},
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},
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};
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@ -118,7 +118,7 @@ static struct clk_alpha_pll gpll9 = {
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.name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_trion_fixed_pll_ops,
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.ops = &clk_alpha_pll_fixed_trion_ops,
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},
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},
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};
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