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remoteproc/mediatek: change MT8192 CFG register base 

The correct MT8192 CFG register base is 0x20000 off.  Changes the
registers accordingly.

Fixes: fd0b6c1ff8 ("remoteproc/mediatek: Add support for mt8192 SCP")
Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20201210054109.587795-1-tzungbi@google.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Tzung-Bi Shih 2020-12-10 13:41:09 +08:00 committed by Bjorn Andersson
parent b44786c9bd
commit 0a441514bc
1 changed files with 12 additions and 12 deletions
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24
drivers/remoteproc/mtk_common.h
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@ -32,22 +32,22 @@
#define MT8183_SCP_CACHESIZE_8KB BIT(8)
#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
#define MT8192_L2TCM_SRAM_PD_0 0x210C0
#define MT8192_L2TCM_SRAM_PD_1 0x210C4
#define MT8192_L2TCM_SRAM_PD_2 0x210C8
#define MT8192_L1TCM_SRAM_PDN 0x2102C
#define MT8192_CPU0_SRAM_PD 0x21080
#define MT8192_L2TCM_SRAM_PD_0 0x10C0
#define MT8192_L2TCM_SRAM_PD_1 0x10C4
#define MT8192_L2TCM_SRAM_PD_2 0x10C8
#define MT8192_L1TCM_SRAM_PDN 0x102C
#define MT8192_CPU0_SRAM_PD 0x1080
#define MT8192_SCP2APMCU_IPC_SET 0x24080
#define MT8192_SCP2APMCU_IPC_CLR 0x24084
#define MT8192_SCP2APMCU_IPC_SET 0x4080
#define MT8192_SCP2APMCU_IPC_CLR 0x4084
#define MT8192_SCP_IPC_INT_BIT BIT(0)
#define MT8192_SCP2SPM_IPC_CLR 0x24094
#define MT8192_GIPC_IN_SET 0x24098
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
#define MT8192_CORE0_SW_RSTN_CLR 0x30000
#define MT8192_CORE0_SW_RSTN_SET 0x30004
#define MT8192_CORE0_WDT_CFG 0x30034
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
#define MT8192_CORE0_WDT_CFG 0x10034
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288