spelling fixes: arch/sh64/
Spelling fixes in arch/sh64/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -4,7 +4,7 @@
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* May be copied or modified under the terms of the GNU General Public
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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* License. See linux/COPYING for more information.
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*
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*
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* Defintions for the SH5 PCI hardware.
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* Definitions for the SH5 PCI hardware.
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*/
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*/
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/* Product ID */
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/* Product ID */
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@ -387,7 +387,7 @@ ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *))
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* NOTE! Only a kernel-only process(ie the swapper or direct descendants
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* NOTE! Only a kernel-only process(ie the swapper or direct descendants
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* who haven't done an "execve()") should use this: it will work within
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* who haven't done an "execve()") should use this: it will work within
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* a system call from a "real" process, but the process memory space will
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* a system call from a "real" process, but the process memory space will
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* not be free'd until both the parent and the child have exited.
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* not be freed until both the parent and the child have exited.
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*/
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*/
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int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
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int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
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{
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{
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@ -123,7 +123,7 @@ static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
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static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
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static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
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/* Estimate number of microseconds that have elapsed since the last timer tick,
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/* Estimate number of microseconds that have elapsed since the last timer tick,
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by scaling the delta that has occured in the CTC register.
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by scaling the delta that has occurred in the CTC register.
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WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
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WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
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the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
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the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
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@ -213,7 +213,7 @@ static int __init smsc_superio_setup(void)
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SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
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SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
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#endif
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#endif
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/* Exit the configuraton state */
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/* Exit the configuration state */
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outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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return 0;
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return 0;
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@ -135,7 +135,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
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/* SIM
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/* SIM
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* Note this is now called with interrupts still disabled
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* Note this is now called with interrupts still disabled
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* This is to cope with being called for a missing IO port
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* This is to cope with being called for a missing IO port
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* address with interupts disabled. This should be fixed as
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* address with interrupts disabled. This should be fixed as
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* soon as we have a better 'fast path' miss handler.
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* soon as we have a better 'fast path' miss handler.
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*
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*
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* Plus take care how you try and debug this stuff.
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* Plus take care how you try and debug this stuff.
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@ -14,7 +14,7 @@
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* IMPORTANT NOTES :
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* IMPORTANT NOTES :
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* The do_fast_page_fault function is called from a context in entry.S where very few registers
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* The do_fast_page_fault function is called from a context in entry.S where very few registers
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* have been saved. In particular, the code in this file must be compiled not to use ANY
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* have been saved. In particular, the code in this file must be compiled not to use ANY
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* caller-save regiseters that are not part of the restricted save set. Also, it means that
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* caller-save registers that are not part of the restricted save set. Also, it means that
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* code in this file must not make calls to functions elsewhere in the kernel, or else the
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* code in this file must not make calls to functions elsewhere in the kernel, or else the
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* excepting context will see corruption in its caller-save registers. Plus, the entry.S save
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* excepting context will see corruption in its caller-save registers. Plus, the entry.S save
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* area is non-reentrant, so this code has to run with SR.BL==1, i.e. no interrupts taken inside
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* area is non-reentrant, so this code has to run with SR.BL==1, i.e. no interrupts taken inside
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@ -249,7 +249,7 @@ asmlinkage int do_fast_page_fault(unsigned long long ssr_md, unsigned long long
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/* SIM
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/* SIM
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* Note this is now called with interrupts still disabled
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* Note this is now called with interrupts still disabled
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* This is to cope with being called for a missing IO port
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* This is to cope with being called for a missing IO port
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* address with interupts disabled. This should be fixed as
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* address with interrupts disabled. This should be fixed as
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* soon as we have a better 'fast path' miss handler.
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* soon as we have a better 'fast path' miss handler.
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*
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*
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* Plus take care how you try and debug this stuff.
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* Plus take care how you try and debug this stuff.
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