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drm/amd/display: add support for per-state dummy-pstate latency 

[why]
Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.

[how]
Rather than statically calculating dummy pstate using
worst case, we store the entire table of UCLK to dummy
pstate relationships.  On a per mode basis, we calculate
the actual UCLK lower limit, and use the dynamic worst
case dummy pstate latency.  This prevents the situation
where we don't support full p-state (which will force
high DPM), but still use low DPM dummy pstate latency.

Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jun Lei 2020-05-26 11:17:53 -04:00 committed by Alex Deucher
parent a1500a62d0
commit 0a25e8eb95
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
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@ -198,11 +198,17 @@ struct wm_table {
#endif
};
struct dummy_pstate_entry {
unsigned int dram_speed_mts;
unsigned int dummy_pstate_latency_us;
};
struct clk_bw_params {
unsigned int vram_type;
unsigned int num_channels;
struct clk_limit_table clk_table;
struct wm_table wm_table;
struct dummy_pstate_entry dummy_pstate_table[4];
};
/* Public interfaces */