drm/amdgpu/psp: Add VBIOS flash handler
Add psp vbflash function for psp v13. v2: fix warnings Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -129,6 +129,7 @@ struct psp_funcs
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void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
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int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
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int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
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int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
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};
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#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
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@ -417,6 +418,10 @@ struct amdgpu_psp_funcs {
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((psp)->funcs->read_usbc_pd_fw ? \
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(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
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#define psp_update_spirom(psp, fw_pri_mc_addr) \
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((psp)->funcs->update_spirom ? \
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(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
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extern const struct amd_ip_funcs psp_ip_funcs;
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extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
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@ -50,6 +50,15 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
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/* Read USB-PD from LFB */
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#define GFX_CMD_USB_PD_USE_LFB 0x480
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/* VBIOS gfl defines */
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#define MBOX_READY_MASK 0x80000000
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#define MBOX_STATUS_MASK 0x0000FFFF
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#define MBOX_COMMAND_MASK 0x00FF0000
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#define MBOX_READY_FLAG 0x80000000
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#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
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#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
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#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
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static int psp_v13_0_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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@ -465,6 +474,68 @@ static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
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return ret;
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}
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static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
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{
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uint32_t reg_status = 0, reg_val = 0;
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struct amdgpu_device *adev = psp->adev;
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int ret;
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/* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
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reg_val |= (cmd << 16);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
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/* Ring the doorbell */
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
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MBOX_READY_FLAG, MBOX_READY_MASK, false);
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if (ret) {
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dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
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return ret;
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}
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reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
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if ((reg_status & 0xFFFF) != 0) {
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dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
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cmd, reg_status & 0xFFFF);
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return -EIO;
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}
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return 0;
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}
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int psp_v13_0_update_spirom(struct psp_context *psp, uint64_t fw_pri_mc_addr)
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{
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struct amdgpu_device *adev = psp->adev;
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int ret;
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/* Confirm PSP is ready to start */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
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MBOX_READY_FLAG, MBOX_READY_MASK, false);
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if (ret) {
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dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
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return ret;
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}
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
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ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
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if (ret)
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return ret;
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
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ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
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if (ret)
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return ret;
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ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
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if (ret)
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return ret;
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return 0;
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}
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static const struct psp_funcs psp_v13_0_funcs = {
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.init_microcode = psp_v13_0_init_microcode,
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.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
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@ -481,7 +552,8 @@ static const struct psp_funcs psp_v13_0_funcs = {
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.ring_get_wptr = psp_v13_0_ring_get_wptr,
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.ring_set_wptr = psp_v13_0_ring_set_wptr,
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.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
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.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw
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.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
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.update_spirom = psp_v13_0_update_spirom
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};
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void psp_v13_0_set_psp_funcs(struct psp_context *psp)
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