Samsung PM 3rd updates for v3.19
- exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUdsuOAAoJEA0Cl+kVi2xq4fkP/R4LIcYizfZxpe810YJWcIxU +1Ex5uesn0hgO8SfOaYixeuMyfhTWt4PQzfrFofL/WeQwgEMHeuBCqyWMbzBoF2v oi4U8zE90z8YTsKR31qXfwcZydMpXnqpj9KeIXsh/1S1wvJduKExQ6vgRdzD1cSK t/NXiU3AkvDrAf/NGgbM9bY6+vKpqMGY2OpLjYzouGA+3xObjbSol+aI9xMpagbh AacVwYOUHu+KKQx2A34toGVnrhNo6kPQ+eYR6JMCpHC3cNmysW8JeDCS/GI+dJLe Nu3NEOtPL2E4KsPm+4O44dRkxZVfhWht/+5KhSpyU8OCU7k876iP9HsMDbRRc251 WCoKMCPReZtbR3KDE1xU/qZhiBSe2bMo0EgnZn/rTg4pusbaBgtpmA8dy17hYfLQ YCYMV867Zcq8uZseiuaR6UaSqKPF4jciSq6w56YC3Ozi1DRmo1vKA0VHqYKiWZPm 8iD14+enPj1QNHwlYln2HyyttvreEFeU/wMUKe/qdQhPftrLlNDeliXHy12HZ6K+ eRgC8JmLITQiJ/mVy8yshsLa62S2jdEbWYmlOniTpaELFpgmMGVCBKySXdSh7sVf feaybFIUDjt0IxkKYTceqIpOs+dJ7eP/ccmcokMET8jpw78a1jMSddqt6PJz1ooZ /egKklt67zQuYlpGhWjv =bi8c -----END PGP SIGNATURE----- Merge tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim: - exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 * tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf ARM: EXYNOS: move restart code into pmu driver clk: exynos5440: move restart code into clock driver ARM: EXYNOS: add exynos3250 PMU support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
09ffd948a0
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@ -12,7 +12,6 @@
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#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#include <linux/reboot.h>
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#include <linux/of.h>
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#define EXYNOS3250_SOC_ID 0xE3472000
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@ -137,28 +137,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
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},
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};
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static void exynos_restart(enum reboot_mode mode, const char *cmd)
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{
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struct device_node *np;
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u32 val = 0x1;
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void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
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if (of_machine_is_compatible("samsung,exynos5440")) {
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u32 status;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
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addr = of_iomap(np, 0) + 0xbc;
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status = __raw_readl(addr);
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addr = of_iomap(np, 0) + 0xcc;
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val = __raw_readl(addr);
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val = (val & 0xffff0000) | (status & 0xffff);
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}
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__raw_writel(val, addr);
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}
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static struct platform_device exynos_cpuidle = {
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.name = "exynos_cpuidle",
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#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
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@ -383,7 +361,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
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.init_machine = exynos_dt_machine_init,
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.init_late = exynos_init_late,
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.dt_compat = exynos_dt_compat,
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.restart = exynos_restart,
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.reserve = exynos_reserve,
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.dt_fixup = exynos_dt_fixup,
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MACHINE_END
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@ -11,8 +11,11 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/notifier.h>
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#include <linux/reboot.h>
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#include "exynos-pmu.h"
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@ -22,7 +25,7 @@
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struct exynos_pmu_conf {
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unsigned int offset;
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unsigned int val[NUM_SYS_POWERDOWN];
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u8 val[NUM_SYS_POWERDOWN];
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};
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struct exynos_pmu_data {
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@ -31,6 +34,7 @@ struct exynos_pmu_data {
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void (*pmu_init)(void);
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void (*powerdown_conf)(enum sys_powerdown);
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void (*powerdown_conf_extra)(enum sys_powerdown);
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};
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struct exynos_pmu_context {
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@ -51,6 +55,92 @@ static inline u32 pmu_raw_readl(u32 offset)
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return readl_relaxed(pmu_base_addr + offset);
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}
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static struct exynos_pmu_conf exynos3250_pmu_config[] = {
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/* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
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{ EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
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{ EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
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{ EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
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{ EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} },
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{ EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
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{ EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
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{ EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
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{ EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
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{ EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
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{ EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
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{ EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
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{ EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
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{ PMU_TABLE_END,},
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};
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static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
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/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
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{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
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@ -495,6 +585,44 @@ static struct exynos_pmu_conf exynos5420_pmu_config[] = {
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{ PMU_TABLE_END,},
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};
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static unsigned int const exynos3250_list_feed[] = {
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EXYNOS3_ARM_CORE_OPTION(0),
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EXYNOS3_ARM_CORE_OPTION(1),
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EXYNOS3_ARM_CORE_OPTION(2),
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EXYNOS3_ARM_CORE_OPTION(3),
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EXYNOS3_ARM_COMMON_OPTION,
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EXYNOS3_TOP_PWR_OPTION,
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EXYNOS3_CORE_TOP_PWR_OPTION,
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S5P_CAM_OPTION,
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S5P_MFC_OPTION,
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S5P_G3D_OPTION,
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S5P_LCD0_OPTION,
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S5P_ISP_OPTION,
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};
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static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
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{
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unsigned int i;
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unsigned int tmp;
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/* Enable only SC_FEEDBACK */
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for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
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tmp = pmu_raw_readl(exynos3250_list_feed[i]);
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tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
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tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
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pmu_raw_writel(tmp, exynos3250_list_feed[i]);
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}
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if (mode != SYS_SLEEP)
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return;
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pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
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pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
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pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
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pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
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EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
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}
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static unsigned int const exynos5_list_both_cnt_feed[] = {
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EXYNOS5_ARM_CORE0_OPTION,
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EXYNOS5_ARM_CORE1_OPTION,
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@ -632,6 +760,9 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
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pmu_data->pmu_config[i].offset);
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}
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if (pmu_data->powerdown_conf_extra)
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pmu_data->powerdown_conf_extra(mode);
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if (pmu_data->pmu_config_extra) {
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for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
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pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
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@ -639,6 +770,36 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
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}
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}
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static void exynos3250_pmu_init(void)
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{
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unsigned int value;
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/*
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* To prevent from issuing new bus request form L2 memory system
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* If core status is power down, should be set '1' to L2 power down
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*/
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value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
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value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
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pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
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/* Enable USE_STANDBY_WFI for all CORE */
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pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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/*
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* Set PSHOLD port for output high
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*/
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value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
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value |= S5P_PS_HOLD_OUTPUT_HIGH;
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pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
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/*
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* Enable signal for PSHOLD port
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*/
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value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
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value |= S5P_PS_HOLD_EN;
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pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
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}
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static void exynos5250_pmu_init(void)
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{
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unsigned int value;
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@ -716,6 +877,19 @@ static void exynos5420_pmu_init(void)
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pr_info("EXYNOS5420 PMU initialized\n");
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}
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static int pmu_restart_notify(struct notifier_block *this,
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unsigned long code, void *unused)
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{
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pmu_raw_writel(0x1, EXYNOS_SWRESET);
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|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static const struct exynos_pmu_data exynos3250_pmu_data = {
|
||||
.pmu_config = exynos3250_pmu_config,
|
||||
.pmu_init = exynos3250_pmu_init,
|
||||
.powerdown_conf_extra = exynos3250_powerdown_conf_extra,
|
||||
};
|
||||
|
||||
static const struct exynos_pmu_data exynos4210_pmu_data = {
|
||||
.pmu_config = exynos4210_pmu_config,
|
||||
|
|
@ -747,6 +921,9 @@ static struct exynos_pmu_data exynos5420_pmu_data = {
|
|||
*/
|
||||
static const struct of_device_id exynos_pmu_of_device_ids[] = {
|
||||
{
|
||||
.compatible = "samsung,exynos3250-pmu",
|
||||
.data = &exynos3250_pmu_data,
|
||||
}, {
|
||||
.compatible = "samsung,exynos4210-pmu",
|
||||
.data = &exynos4210_pmu_data,
|
||||
}, {
|
||||
|
|
@ -765,11 +942,20 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = {
|
|||
{ /*sentinel*/ },
|
||||
};
|
||||
|
||||
/*
|
||||
* Exynos PMU restart notifier, handles restart functionality
|
||||
*/
|
||||
static struct notifier_block pmu_restart_handler = {
|
||||
.notifier_call = pmu_restart_notify,
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
static int exynos_pmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pmu_base_addr = devm_ioremap_resource(dev, res);
|
||||
|
|
@ -794,6 +980,10 @@ static int exynos_pmu_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, pmu_context);
|
||||
|
||||
ret = register_restart_handler(&pmu_restart_handler);
|
||||
if (ret)
|
||||
dev_warn(dev, "can't register restart handler err=%d\n", ret);
|
||||
|
||||
dev_dbg(dev, "Exynos PMU Driver probe done\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,7 +19,20 @@
|
|||
#define S5P_CENTRAL_SEQ_OPTION 0x0208
|
||||
|
||||
#define S5P_USE_STANDBY_WFI0 (1 << 16)
|
||||
#define S5P_USE_STANDBY_WFI1 (1 << 17)
|
||||
#define S5P_USE_STANDBY_WFI2 (1 << 19)
|
||||
#define S5P_USE_STANDBY_WFI3 (1 << 20)
|
||||
#define S5P_USE_STANDBY_WFE0 (1 << 24)
|
||||
#define S5P_USE_STANDBY_WFE1 (1 << 25)
|
||||
#define S5P_USE_STANDBY_WFE2 (1 << 27)
|
||||
#define S5P_USE_STANDBY_WFE3 (1 << 28)
|
||||
|
||||
#define S5P_USE_STANDBY_WFI_ALL \
|
||||
(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \
|
||||
S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \
|
||||
S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \
|
||||
S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3)
|
||||
|
||||
#define S5P_USE_DELAYED_RESET_ASSERTION BIT(12)
|
||||
|
||||
#define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n)
|
||||
|
|
@ -154,6 +167,17 @@
|
|||
#define S5P_PAD_RET_EBIA_OPTION 0x3188
|
||||
#define S5P_PAD_RET_EBIB_OPTION 0x31A8
|
||||
|
||||
#define S5P_PS_HOLD_CONTROL 0x330C
|
||||
#define S5P_PS_HOLD_EN (1 << 31)
|
||||
#define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8)
|
||||
|
||||
#define S5P_CAM_OPTION 0x3C08
|
||||
#define S5P_MFC_OPTION 0x3C48
|
||||
#define S5P_G3D_OPTION 0x3C68
|
||||
#define S5P_LCD0_OPTION 0x3C88
|
||||
#define S5P_LCD1_OPTION 0x3CA8
|
||||
#define S5P_ISP_OPTION S5P_LCD1_OPTION
|
||||
|
||||
#define S5P_CORE_LOCAL_PWR_EN 0x3
|
||||
#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8)
|
||||
|
||||
|
|
@ -214,6 +238,110 @@
|
|||
#define S5P_DIS_IRQ_CORE3 0x1034
|
||||
#define S5P_DIS_IRQ_CENTRAL3 0x1038
|
||||
|
||||
/* Only for EXYNOS3XXX */
|
||||
#define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000
|
||||
#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
|
||||
#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
|
||||
#define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010
|
||||
#define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
|
||||
#define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
|
||||
#define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050
|
||||
#define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
|
||||
#define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
|
||||
#define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080
|
||||
#define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0
|
||||
#define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
|
||||
#define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
|
||||
#define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C
|
||||
#define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110
|
||||
#define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114
|
||||
#define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C
|
||||
#define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120
|
||||
#define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124
|
||||
#define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128
|
||||
#define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C
|
||||
#define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130
|
||||
#define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134
|
||||
#define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138
|
||||
#define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140
|
||||
#define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148
|
||||
#define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C
|
||||
#define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150
|
||||
#define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154
|
||||
#define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158
|
||||
#define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160
|
||||
#define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168
|
||||
#define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C
|
||||
#define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170
|
||||
#define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174
|
||||
#define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178
|
||||
#define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180
|
||||
#define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184
|
||||
#define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188
|
||||
#define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190
|
||||
#define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194
|
||||
#define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198
|
||||
#define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0
|
||||
#define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4
|
||||
#define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0
|
||||
#define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4
|
||||
#define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
|
||||
#define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204
|
||||
#define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208
|
||||
#define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218
|
||||
#define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
|
||||
#define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
|
||||
#define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228
|
||||
#define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C
|
||||
#define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
|
||||
#define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
|
||||
#define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238
|
||||
#define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240
|
||||
#define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260
|
||||
#define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280
|
||||
#define EXYNOS3_XXTI_SYS_PWR_REG 0x1284
|
||||
#define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0
|
||||
#define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4
|
||||
#define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300
|
||||
#define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340
|
||||
#define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344
|
||||
#define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
|
||||
#define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350
|
||||
#define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354
|
||||
#define EXYNOS3_CAM_SYS_PWR_REG 0x1380
|
||||
#define EXYNOS3_MFC_SYS_PWR_REG 0x1388
|
||||
#define EXYNOS3_G3D_SYS_PWR_REG 0x138C
|
||||
#define EXYNOS3_LCD0_SYS_PWR_REG 0x1390
|
||||
#define EXYNOS3_ISP_SYS_PWR_REG 0x1394
|
||||
#define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398
|
||||
#define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0
|
||||
#define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4
|
||||
#define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8
|
||||
#define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0
|
||||
#define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4
|
||||
#define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8
|
||||
|
||||
#define EXYNOS3_ARM_CORE0_OPTION 0x2008
|
||||
#define EXYNOS3_ARM_CORE_OPTION(_nr) \
|
||||
(EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
|
||||
|
||||
#define EXYNOS3_ARM_COMMON_OPTION 0x2408
|
||||
#define EXYNOS3_TOP_PWR_OPTION 0x2C48
|
||||
#define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8
|
||||
#define EXYNOS3_XUSBXTI_DURATION 0x341C
|
||||
#define EXYNOS3_XXTI_DURATION 0x343C
|
||||
#define EXYNOS3_EXT_REGULATOR_DURATION 0x361C
|
||||
#define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C
|
||||
#define XUSBXTI_DURATION 0x00000BB8
|
||||
#define XXTI_DURATION XUSBXTI_DURATION
|
||||
#define EXT_REGULATOR_DURATION 0x00001D4C
|
||||
#define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION
|
||||
|
||||
/* for XXX_OPTION */
|
||||
#define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0)
|
||||
#define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1)
|
||||
#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
|
||||
|
||||
/* For EXYNOS5 */
|
||||
|
||||
#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
|
@ -23,6 +25,8 @@
|
|||
#define CPU_CLK_STATUS 0xfc
|
||||
#define MISC_DOUT1 0x558
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
/* parent clock name list */
|
||||
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
|
||||
PNAME(mout_spi_p) = { "div125", "div200" };
|
||||
|
|
@ -89,10 +93,30 @@ static const struct of_device_id ext_clk_match[] __initconst = {
|
|||
{},
|
||||
};
|
||||
|
||||
static int exynos5440_clk_restart_notify(struct notifier_block *this,
|
||||
unsigned long code, void *unused)
|
||||
{
|
||||
u32 val, status;
|
||||
|
||||
status = readl_relaxed(reg_base + 0xbc);
|
||||
val = readl_relaxed(reg_base + 0xcc);
|
||||
val = (val & 0xffff0000) | (status & 0xffff);
|
||||
writel_relaxed(val, reg_base + 0xcc);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Exynos5440 Clock restart notifier, handles restart functionality
|
||||
*/
|
||||
static struct notifier_block exynos5440_clk_restart_handler = {
|
||||
.notifier_call = exynos5440_clk_restart_notify,
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
/* register exynos5440 clocks */
|
||||
static void __init exynos5440_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
|
|
@ -125,6 +149,9 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
|||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
if (register_restart_handler(&exynos5440_clk_restart_handler))
|
||||
pr_warn("exynos5440 clock can't register restart handler\n");
|
||||
|
||||
pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
|
||||
pr_info("exynos5440 clock initialization complete\n");
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue