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drm/amd/display: Change min_h_sync_width from 8 to 4 

[Why]
Some display's hsync width is lower than the minimum dcn20 is set
to support right now. This will cause optc1_validate_timing to fail which
eventually will result in wrong set mode. This was set to 8 as per
HW team's request for no valid reason.

[How]
Changing min_h_sync_width to 4 will let us validate timing for
preffered mode and light up the headset. This change was made
to Vega 10 before for a similar issue.

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fatemeh Darbehani 2019-06-21 17:44:50 -04:00 committed by Alex Deucher
parent 74eda776d7
commit 09fc26c171
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
View File

@ -535,7 +535,7 @@ void dcn20_timing_generator_init(struct optc *optc1)
optc1->min_h_blank = 32; optc1->min_h_blank = 32;
optc1->min_v_blank = 3; optc1->min_v_blank = 3;
optc1->min_v_blank_interlace = 5; optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 8; optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
optc1->min_v_sync_width = 1; optc1->min_v_sync_width = 1;
optc1->comb_opp_id = 0xf; optc1->comb_opp_id = 0xf;
} }