drm/amdgpu: query vram_width from vram_info table
Driver will get channel_number and channel_width from vram_info table, then calculate vram_width by multiply channel_number by channel_width Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -127,23 +127,51 @@ union vram_info {
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int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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integratedsysteminfo);
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int index;
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u16 data_offset, size;
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union igp_info *igp_info;
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union vram_info *vram_info;
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u32 mem_channel_number;
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u32 mem_channel_width;
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u8 frev, crev;
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if (adev->flags & AMD_IS_APU)
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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integratedsysteminfo);
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else
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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vram_info);
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/* get any igp specific overrides */
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
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&frev, &crev, &data_offset)) {
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if (adev->flags & AMD_IS_APU) {
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igp_info = (union igp_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 11:
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return igp_info->v11.umachannelnumber * 64;
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mem_channel_number = igp_info->v11.umachannelnumber;
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/* channel width is 64 */
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return mem_channel_number * 64;
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default:
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return 0;
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}
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} else {
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vram_info = (union vram_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 3:
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mem_channel_number = vram_info->v23.vram_module[0].channel_num;
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mem_channel_width = vram_info->v23.vram_module[0].channel_width;
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return mem_channel_number * (1 << mem_channel_width);
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case 4:
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mem_channel_number = vram_info->v24.vram_module[0].channel_num;
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mem_channel_width = vram_info->v24.vram_module[0].channel_width;
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return mem_channel_number * (1 << mem_channel_width);
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default:
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return 0;
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}
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}
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}
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return 0;
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