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drm/nouveau/dma: switch to instanced constructor 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 15:21:35 +10:00
parent a7f000ec56
commit 09f409d74d
12 changed files with 111 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_dma *dma;
struct nvkm_fifo *fifo;
struct nvkm_gr *gr;
struct nvkm_engine *ifb;
@ -118,7 +117,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*dma )(struct nvkm_device *, int idx, struct nvkm_dma **);
int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -29,4 +29,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp)
NVKM_LAYOUT_INST(NVKM_ENGINE_CE , struct nvkm_engine , ce, 9)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_CIPHER , struct nvkm_engine , cipher)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DISP , struct nvkm_disp , disp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DMAOBJ , struct nvkm_dma , dma)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

10
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
View File

@ -23,9 +23,9 @@ struct nvkm_dma {
struct nvkm_dmaobj *nvkm_dmaobj_search(struct nvkm_client *, u64 object);
int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int gv100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
int nv04_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
int nv50_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
int gf100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
int gf119_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
int gv100_dma_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_dma **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_DMAOBJ ] = "dma",
[NVKM_ENGINE_FIFO ] = "fifo",
[NVKM_ENGINE_GR ] = "gr",
[NVKM_ENGINE_IFB ] = "ifb",

173
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -89,7 +89,7 @@ nv4_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv04_fifo_new,
.gr = nv04_gr_new,
.sw = nv04_sw_new,
@ -110,7 +110,7 @@ nv5_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv04_fifo_new,
.gr = nv04_gr_new,
.sw = nv04_sw_new,
@ -132,7 +132,7 @@ nv10_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.gr = nv10_gr_new,
};
@ -152,7 +152,7 @@ nv11_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.gr = nv15_gr_new,
.sw = nv10_sw_new,
@ -174,7 +174,7 @@ nv15_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.gr = nv15_gr_new,
.sw = nv10_sw_new,
@ -196,7 +196,7 @@ nv17_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv17_gr_new,
.sw = nv10_sw_new,
@ -218,7 +218,7 @@ nv18_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv17_gr_new,
.sw = nv10_sw_new,
@ -240,7 +240,7 @@ nv1a_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.gr = nv15_gr_new,
.sw = nv10_sw_new,
@ -262,7 +262,7 @@ nv1f_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv17_gr_new,
.sw = nv10_sw_new,
@ -284,7 +284,7 @@ nv20_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv20_gr_new,
.sw = nv10_sw_new,
@ -306,7 +306,7 @@ nv25_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv25_gr_new,
.sw = nv10_sw_new,
@ -328,7 +328,7 @@ nv28_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv25_gr_new,
.sw = nv10_sw_new,
@ -350,7 +350,7 @@ nv2a_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv2a_gr_new,
.sw = nv10_sw_new,
@ -372,7 +372,7 @@ nv30_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv30_gr_new,
.sw = nv10_sw_new,
@ -394,7 +394,7 @@ nv31_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv30_gr_new,
.mpeg = nv31_mpeg_new,
@ -417,7 +417,7 @@ nv34_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv34_gr_new,
.mpeg = nv31_mpeg_new,
@ -440,7 +440,7 @@ nv35_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv35_gr_new,
.sw = nv10_sw_new,
@ -462,7 +462,7 @@ nv36_chipset = {
.pci = { 0x00000001, nv04_pci_new },
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.gr = nv35_gr_new,
.mpeg = nv31_mpeg_new,
@ -487,7 +487,7 @@ nv40_chipset = {
.timer = { 0x00000001, nv40_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
@ -513,7 +513,7 @@ nv41_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
@ -539,7 +539,7 @@ nv42_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
@ -565,7 +565,7 @@ nv43_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
@ -591,7 +591,7 @@ nv44_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -617,7 +617,7 @@ nv45_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
@ -643,7 +643,7 @@ nv46_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -669,7 +669,7 @@ nv47_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
@ -695,7 +695,7 @@ nv49_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
@ -721,7 +721,7 @@ nv4a_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -747,7 +747,7 @@ nv4b_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
@ -773,7 +773,7 @@ nv4c_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -799,7 +799,7 @@ nv4e_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -828,7 +828,7 @@ nv50_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv50_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = nv50_fifo_new,
.gr = nv50_gr_new,
.mpeg = nv50_mpeg_new,
@ -854,7 +854,7 @@ nv63_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -880,7 +880,7 @@ nv67_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -906,7 +906,7 @@ nv68_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = nv04_dma_new,
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
@ -937,7 +937,7 @@ nv84_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
@ -969,7 +969,7 @@ nv86_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
@ -1001,7 +1001,7 @@ nv92_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
@ -1033,7 +1033,7 @@ nv94_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g94_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
@ -1065,7 +1065,7 @@ nv96_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g94_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
@ -1095,7 +1095,7 @@ nv98_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, g94_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.mspdec = g98_mspdec_new,
@ -1129,7 +1129,7 @@ nva0_chipset = {
.bsp = { 0x00000001, g84_bsp_new },
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, gt200_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = gt200_gr_new,
.mpeg = g84_mpeg_new,
@ -1161,7 +1161,7 @@ nva3_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = gt215_gr_new,
.mpeg = g84_mpeg_new,
@ -1195,7 +1195,7 @@ nva5_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
@ -1228,7 +1228,7 @@ nva8_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
@ -1259,7 +1259,7 @@ nvaa_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, mcp77_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = gt200_gr_new,
.mspdec = g98_mspdec_new,
@ -1291,7 +1291,7 @@ nvac_chipset = {
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, mcp77_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = mcp79_gr_new,
.mspdec = g98_mspdec_new,
@ -1325,7 +1325,7 @@ nvaf_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, mcp89_disp_new },
.dma = nv50_dma_new,
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.gr = mcp89_gr_new,
.mspdec = gt215_mspdec_new,
@ -1361,7 +1361,7 @@ nvc0_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf100_gr_new,
.mspdec = gf100_mspdec_new,
@ -1397,7 +1397,7 @@ nvc1_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf108_gr_new,
.mspdec = gf100_mspdec_new,
@ -1433,7 +1433,7 @@ nvc3_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
@ -1469,7 +1469,7 @@ nvc4_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
@ -1505,7 +1505,7 @@ nvc8_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf110_gr_new,
.mspdec = gf100_mspdec_new,
@ -1541,7 +1541,7 @@ nvce_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
@ -1577,7 +1577,7 @@ nvcf_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = gf100_dma_new,
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
@ -1612,7 +1612,7 @@ nvd7_chipset = {
.volt = { 0x00000001, gf117_volt_new },
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gf119_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gf100_fifo_new,
.gr = gf117_gr_new,
.mspdec = gf100_mspdec_new,
@ -1648,7 +1648,7 @@ nvd9_chipset = {
.volt = { 0x00000001, gf100_volt_new },
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gf119_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gf100_fifo_new,
.gr = gf119_gr_new,
.mspdec = gf100_mspdec_new,
@ -1685,7 +1685,7 @@ nve4_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
@ -1722,7 +1722,7 @@ nve6_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
@ -1759,7 +1759,7 @@ nve7_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
@ -1787,7 +1787,7 @@ nvea_chipset = {
.top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gk20a_volt_new },
.ce = { 0x00000004, gk104_ce_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk20a_fifo_new,
.gr = gk20a_gr_new,
.pm = gk104_pm_new,
@ -1821,7 +1821,7 @@ nvf0_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk110_fifo_new,
.gr = gk110_gr_new,
.mspdec = gk104_mspdec_new,
@ -1857,7 +1857,7 @@ nvf1_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk110_fifo_new,
.gr = gk110b_gr_new,
.mspdec = gk104_mspdec_new,
@ -1893,7 +1893,7 @@ nv106_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk208_fifo_new,
.gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
@ -1929,7 +1929,7 @@ nv108_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk208_fifo_new,
.gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
@ -1965,7 +1965,7 @@ nv117_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000005, gm107_ce_new },
.disp = { 0x00000001, gm107_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm107_fifo_new,
.gr = gm107_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2000,7 +2000,7 @@ nv118_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000005, gm107_ce_new },
.disp = { 0x00000001, gm107_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm107_fifo_new,
.gr = gm107_gr_new,
.sw = gf100_sw_new,
@ -2033,7 +2033,7 @@ nv120_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2069,7 +2069,7 @@ nv124_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2105,7 +2105,7 @@ nv126_chipset = {
.volt = { 0x00000001, gk104_volt_new },
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2132,7 +2132,7 @@ nv12b_chipset = {
.top = { 0x00000001, gk104_top_new },
.volt = { 0x00000001, gm20b_volt_new },
.ce = { 0x00000004, gm200_ce_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm20b_fifo_new,
.gr = gm20b_gr_new,
.sw = gf100_sw_new,
@ -2162,7 +2162,7 @@ nv130_chipset = {
.timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000003f, gp100_ce_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.disp = { 0x00000001, gp100_disp_new },
.fifo = gp100_fifo_new,
.gr = gp100_gr_new,
@ -2198,7 +2198,7 @@ nv132_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.gr = gp102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2233,7 +2233,7 @@ nv134_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.gr = gp104_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2268,7 +2268,7 @@ nv136_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.gr = gp104_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2302,7 +2302,7 @@ nv137_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.gr = gp107_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2337,7 +2337,7 @@ nv138_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.gr = gp108_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2363,7 +2363,7 @@ nv13b_chipset = {
.timer = { 0x00000001, gk20a_timer_new },
.top = { 0x00000001, gk104_top_new },
.ce = { 0x00000001, gp100_ce_new },
.dma = gf119_dma_new,
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp10b_fifo_new,
.gr = gp10b_gr_new,
.sw = gf100_sw_new,
@ -2395,7 +2395,7 @@ nv140_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x000001ff, gv100_ce_new },
.disp = { 0x00000001, gv100_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = gv100_fifo_new,
.gr = gv100_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2431,7 +2431,7 @@ nv162_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2465,7 +2465,7 @@ nv164_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2500,7 +2500,7 @@ nv166_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2536,7 +2536,7 @@ nv167_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2570,7 +2570,7 @@ nv168_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
@ -2611,7 +2611,7 @@ nv172_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.disp = { 0x00000001, ga102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
};
static const struct nvkm_device_chip
@ -2630,7 +2630,7 @@ nv174_chipset = {
.pci = { 0x00000001, gp100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.disp = { 0x00000001, ga102_disp_new },
.dma = gv100_dma_new,
.dma = { 0x00000001, gv100_dma_new },
};
static int
@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_DMAOBJ , dma);
_(NVKM_ENGINE_FIFO , fifo);
_(NVKM_ENGINE_GR , gr);
_(NVKM_ENGINE_IFB , ifb);

4
drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
View File

@ -104,7 +104,7 @@ nvkm_dma = {
int
nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device,
int index, struct nvkm_dma **pdma)
enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma)
{
struct nvkm_dma *dma;
@ -112,5 +112,5 @@ nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device,
return -ENOMEM;
dma->func = func;
return nvkm_engine_ctor(&nvkm_dma, device, index, true, &dma->engine);
return nvkm_engine_ctor(&nvkm_dma, device, type, inst, true, &dma->engine);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
View File

@ -30,7 +30,8 @@ gf100_dma = {
};
int
gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
gf100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&gf100_dma, device, index, pdma);
return nvkm_dma_new_(&gf100_dma, device, type, inst, pdma);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c
View File

@ -30,7 +30,8 @@ gf119_dma = {
};
int
gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
gf119_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&gf119_dma, device, index, pdma);
return nvkm_dma_new_(&gf119_dma, device, type, inst, pdma);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.c
View File

@ -28,7 +28,8 @@ gv100_dma = {
};
int
gv100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
gv100_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&gv100_dma, device, index, pdma);
return nvkm_dma_new_(&gv100_dma, device, type, inst, pdma);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
View File

@ -30,7 +30,8 @@ nv04_dma = {
};
int
nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
nv04_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&nv04_dma, device, index, pdma);
return nvkm_dma_new_(&nv04_dma, device, type, inst, pdma);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
View File

@ -30,7 +30,8 @@ nv50_dma = {
};
int
nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
nv50_dma_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_dma **pdma)
{
return nvkm_dma_new_(&nv50_dma, device, index, pdma);
return nvkm_dma_new_(&nv50_dma, device, type, inst, pdma);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h
View File

@ -9,8 +9,8 @@ struct nvkm_dmaobj_func {
struct nvkm_gpuobj **);
};
int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *,
int index, struct nvkm_dma **);
int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_dma **);
struct nvkm_dma_func {
int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *,