iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
For T5, we must not use the kdb/kgts registers, in order avoid db drops under extreme loads. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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@ -156,12 +156,19 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
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goto err4;
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cq->gen = 1;
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cq->gts = rdev->lldi.gts_reg;
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cq->rdev = rdev;
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if (user) {
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cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
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(cq->cqid << rdev->cqshift);
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cq->ugts &= PAGE_MASK;
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u32 off = (cq->cqid << rdev->cqshift) & PAGE_MASK;
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cq->ugts = (u64)rdev->bar2_pa + off;
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} else if (is_t4(rdev->lldi.adapter_type)) {
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cq->gts = rdev->lldi.gts_reg;
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cq->qid_mask = -1U;
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} else {
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u32 off = ((cq->cqid << rdev->cqshift) & PAGE_MASK) + 12;
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cq->gts = rdev->bar2_kva + off;
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cq->qid_mask = rdev->qpmask;
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}
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return 0;
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err4:
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@ -539,6 +539,7 @@ struct t4_cq {
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size_t memsize;
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__be64 bits_type_ts;
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u32 cqid;
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u32 qid_mask;
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int vector;
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u16 size; /* including status page */
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u16 cidx;
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@ -563,12 +564,12 @@ static inline int t4_arm_cq(struct t4_cq *cq, int se)
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set_bit(CQ_ARMED, &cq->flags);
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while (cq->cidx_inc > CIDXINC_M) {
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val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7) |
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INGRESSQID_V(cq->cqid);
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INGRESSQID_V(cq->cqid & cq->qid_mask);
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writel(val, cq->gts);
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cq->cidx_inc -= CIDXINC_M;
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}
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val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6) |
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INGRESSQID_V(cq->cqid);
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INGRESSQID_V(cq->cqid & cq->qid_mask);
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writel(val, cq->gts);
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cq->cidx_inc = 0;
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return 0;
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@ -601,7 +602,7 @@ static inline void t4_hwcq_consume(struct t4_cq *cq)
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u32 val;
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val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7) |
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INGRESSQID_V(cq->cqid);
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INGRESSQID_V(cq->cqid & cq->qid_mask);
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writel(val, cq->gts);
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cq->cidx_inc = 0;
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}
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