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mmc: sdhci-esdhc-imx: support eMMC DDR mode when running at 3.3V 

The uSDHC supports DDR modes for eMMC devices running at 3.3V. This
allows to run eMMC with 3.3V signaling voltage at DDR52 mode:

  # cat /sys/kernel/debug/mmc1/ios
  clock:          52000000 Hz
  vdd:            21 (3.3 ~ 3.4 V)
  bus mode:       2 (push-pull)
  chip select:    0 (don't care)
  power mode:     2 (on)
  bus width:      3 (8 bits)
  timing spec:    8 (mmc DDR52)
  signal voltage: 0 (3.30 V)
  driver type:    0 (driver type B)

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Stefan Agner 2018-06-28 09:31:36 +02:00 committed by Ulf Hansson
parent 29772f8a73
commit 09c8192be7
1 changed files with 1 additions and 1 deletions
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2
drivers/mmc/host/sdhci-esdhc-imx.c
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@ -1318,7 +1318,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
if (esdhc_is_usdhc(imx_data)) {
host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host->mmc->caps |= MMC_CAP_1_8V_DDR;
host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;