EDAC: altera: merge ARCH_SOCFPGA and ARCH_STRATIX10
Simplify 32-bit and 64-bit Intel SoCFPGA Kconfig options by having only one for both of them. This the common practice for other platforms. Additionally, the ARCH_SOCFPGA is too generic as SoCFPGA designs come from multiple vendors. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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2011431b97
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@ -396,7 +396,7 @@ config EDAC_THUNDERX
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config EDAC_ALTERA
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config EDAC_ALTERA
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bool "Altera SOCFPGA ECC"
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bool "Altera SOCFPGA ECC"
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depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
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depends on EDAC=y && ARCH_INTEL_SOCFPGA
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help
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help
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Support for error detection and correction on the
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Support for error detection and correction on the
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Altera SOCs. This is the global enable for the
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Altera SOCs. This is the global enable for the
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@ -1501,8 +1501,13 @@ static int altr_portb_setup(struct altr_edac_device_dev *device)
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dci->mod_name = ecc_name;
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dci->mod_name = ecc_name;
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dci->dev_name = ecc_name;
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dci->dev_name = ecc_name;
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/* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
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/*
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#ifdef CONFIG_ARCH_STRATIX10
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* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
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*
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* FIXME: Instead of ifdefs with different architectures the driver
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* should properly use compatibles.
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*/
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#ifdef CONFIG_64BIT
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altdev->sb_irq = irq_of_parse_and_map(np, 1);
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altdev->sb_irq = irq_of_parse_and_map(np, 1);
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#else
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#else
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altdev->sb_irq = irq_of_parse_and_map(np, 2);
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altdev->sb_irq = irq_of_parse_and_map(np, 2);
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@ -1521,7 +1526,7 @@ static int altr_portb_setup(struct altr_edac_device_dev *device)
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goto err_release_group_1;
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goto err_release_group_1;
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}
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}
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#ifdef CONFIG_ARCH_STRATIX10
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#ifdef CONFIG_64BIT
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/* Use IRQ to determine SError origin instead of assigning IRQ */
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/* Use IRQ to determine SError origin instead of assigning IRQ */
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rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
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rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
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if (rc) {
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if (rc) {
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@ -1931,7 +1936,7 @@ static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
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goto err_release_group1;
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goto err_release_group1;
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}
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}
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#ifdef CONFIG_ARCH_STRATIX10
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#ifdef CONFIG_64BIT
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/* Use IRQ to determine SError origin instead of assigning IRQ */
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/* Use IRQ to determine SError origin instead of assigning IRQ */
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rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
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rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
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if (rc) {
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if (rc) {
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@ -2016,7 +2021,7 @@ static const struct irq_domain_ops a10_eccmgr_ic_ops = {
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/************** Stratix 10 EDAC Double Bit Error Handler ************/
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/************** Stratix 10 EDAC Double Bit Error Handler ************/
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#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
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#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
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#ifdef CONFIG_ARCH_STRATIX10
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#ifdef CONFIG_64BIT
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/* panic routine issues reboot on non-zero panic_timeout */
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/* panic routine issues reboot on non-zero panic_timeout */
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extern int panic_timeout;
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extern int panic_timeout;
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@ -2109,7 +2114,7 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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altr_edac_a10_irq_handler,
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altr_edac_a10_irq_handler,
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edac);
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edac);
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#ifdef CONFIG_ARCH_STRATIX10
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#ifdef CONFIG_64BIT
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{
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{
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int dberror, err_addr;
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int dberror, err_addr;
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