ARM: S5PV310: Add support SROMC
This patch adds support SROMC for S5PV310 and S5PC210. Signed-off-by: Daein Moon <moon9124@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -77,6 +77,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_512K,
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.length = SZ_512K,
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.type = MT_DEVICE,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(S5PV310_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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},
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};
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};
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@ -25,6 +25,8 @@
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#define S5PV310_PA_SYSRAM (0x02025000)
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#define S5PV310_PA_SYSRAM (0x02025000)
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#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
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#define S5PC210_PA_ONENAND (0x0C000000)
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#define S5PC210_PA_ONENAND (0x0C000000)
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#define S5P_PA_ONENAND S5PC210_PA_ONENAND
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#define S5P_PA_ONENAND S5PC210_PA_ONENAND
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@ -56,6 +58,8 @@
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#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
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#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
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#define S5PV310_PA_SROMC (0x12570000)
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#define S5PV310_PA_UART (0x13800000)
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#define S5PV310_PA_UART (0x13800000)
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#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
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#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
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@ -0,0 +1,50 @@
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/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 - SROMC register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_SROM_H
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#define __ASM_ARCH_REGS_SROM_H __FILE__
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#include <mach/map.h>
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#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
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#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
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#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
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#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
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#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
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#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
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#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
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#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
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#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
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#define S5PV310_SROM_BW__CS_MASK 0xf
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#define S5PV310_SROM_BW__NCS0__SHIFT 0
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#define S5PV310_SROM_BW__NCS1__SHIFT 4
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#define S5PV310_SROM_BW__NCS2__SHIFT 8
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#define S5PV310_SROM_BW__NCS3__SHIFT 12
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/* applies to same to BCS0 - BCS3 */
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#define S5PV310_SROM_BCX__PMC__SHIFT 0
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#define S5PV310_SROM_BCX__TACP__SHIFT 4
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#define S5PV310_SROM_BCX__TCAH__SHIFT 8
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#define S5PV310_SROM_BCX__TCOH__SHIFT 12
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#define S5PV310_SROM_BCX__TACC__SHIFT 16
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#define S5PV310_SROM_BCX__TCOS__SHIFT 24
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#define S5PV310_SROM_BCX__TACS__SHIFT 28
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#endif /* __ASM_ARCH_REGS_SROM_H */
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