mt76: mt7921: fixup rx bitrate statistics
Since the related rx bitrate fields have been moved to group3 in Rxv,
fix rx bitrate statistics in mt7921_mac_fill_rx routine.
Fixes: 163f4d22c1
("mt76: mt7921: add MAC support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
a7e3033fcd
commit
0940605a2a
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@ -400,7 +400,9 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
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/* RXD Group 3 - P-RXV */
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if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
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u32 v0, v1, v2;
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u8 stbc, gi;
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u32 v0, v1;
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bool cck;
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rxv = rxd;
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rxd += 2;
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@ -409,7 +411,6 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
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v0 = le32_to_cpu(rxv[0]);
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v1 = le32_to_cpu(rxv[1]);
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v2 = le32_to_cpu(rxv[2]);
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if (v0 & MT_PRXV_HT_AD_CODE)
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status->enc_flags |= RX_ENC_FLAG_LDPC;
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@ -429,87 +430,87 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
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status->chain_signal[i]);
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}
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/* RXD Group 5 - C-RXV */
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if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
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u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
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u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
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bool cck = false;
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stbc = FIELD_GET(MT_PRXV_STBC, v0);
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gi = FIELD_GET(MT_PRXV_SGI, v0);
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cck = false;
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idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
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mode = FIELD_GET(MT_PRXV_TX_MODE, v0);
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switch (mode) {
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case MT_PHY_TYPE_CCK:
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cck = true;
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fallthrough;
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case MT_PHY_TYPE_OFDM:
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i = mt76_get_rate(&dev->mt76, sband, i, cck);
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break;
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case MT_PHY_TYPE_HT_GF:
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case MT_PHY_TYPE_HT:
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status->encoding = RX_ENC_HT;
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if (i > 31)
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return -EINVAL;
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break;
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case MT_PHY_TYPE_VHT:
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status->nss =
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FIELD_GET(MT_PRXV_NSTS, v0) + 1;
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status->encoding = RX_ENC_VHT;
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if (i > 9)
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return -EINVAL;
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break;
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case MT_PHY_TYPE_HE_MU:
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status->flag |= RX_FLAG_RADIOTAP_HE_MU;
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fallthrough;
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case MT_PHY_TYPE_HE_SU:
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case MT_PHY_TYPE_HE_EXT_SU:
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case MT_PHY_TYPE_HE_TB:
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status->nss =
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FIELD_GET(MT_PRXV_NSTS, v0) + 1;
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status->encoding = RX_ENC_HE;
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status->flag |= RX_FLAG_RADIOTAP_HE;
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i &= GENMASK(3, 0);
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if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
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status->he_gi = gi;
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status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
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break;
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default:
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return -EINVAL;
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}
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status->rate_idx = i;
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switch (FIELD_GET(MT_PRXV_FRAME_MODE, v0)) {
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case IEEE80211_STA_RX_BW_20:
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break;
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case IEEE80211_STA_RX_BW_40:
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if (mode & MT_PHY_TYPE_HE_EXT_SU &&
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(idx & MT_PRXV_TX_ER_SU_106T)) {
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status->bw = RATE_INFO_BW_HE_RU;
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status->he_ru =
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NL80211_RATE_INFO_HE_RU_ALLOC_106;
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} else {
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status->bw = RATE_INFO_BW_40;
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}
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break;
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case IEEE80211_STA_RX_BW_80:
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status->bw = RATE_INFO_BW_80;
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break;
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case IEEE80211_STA_RX_BW_160:
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status->bw = RATE_INFO_BW_160;
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break;
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default:
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return -EINVAL;
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}
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status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
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if (mode < MT_PHY_TYPE_HE_SU && gi)
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status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
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if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
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rxd += 18;
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if ((u8 *)rxd - skb->data >= skb->len)
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return -EINVAL;
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idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
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mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
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switch (mode) {
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case MT_PHY_TYPE_CCK:
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cck = true;
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fallthrough;
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case MT_PHY_TYPE_OFDM:
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i = mt76_get_rate(&dev->mt76, sband, i, cck);
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break;
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case MT_PHY_TYPE_HT_GF:
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case MT_PHY_TYPE_HT:
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status->encoding = RX_ENC_HT;
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if (i > 31)
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return -EINVAL;
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break;
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case MT_PHY_TYPE_VHT:
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status->nss =
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FIELD_GET(MT_PRXV_NSTS, v0) + 1;
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status->encoding = RX_ENC_VHT;
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if (i > 9)
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return -EINVAL;
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break;
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case MT_PHY_TYPE_HE_MU:
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status->flag |= RX_FLAG_RADIOTAP_HE_MU;
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fallthrough;
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case MT_PHY_TYPE_HE_SU:
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case MT_PHY_TYPE_HE_EXT_SU:
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case MT_PHY_TYPE_HE_TB:
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status->nss =
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FIELD_GET(MT_PRXV_NSTS, v0) + 1;
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status->encoding = RX_ENC_HE;
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status->flag |= RX_FLAG_RADIOTAP_HE;
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i &= GENMASK(3, 0);
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if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
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status->he_gi = gi;
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status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
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break;
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default:
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return -EINVAL;
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}
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status->rate_idx = i;
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switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
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case IEEE80211_STA_RX_BW_20:
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break;
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case IEEE80211_STA_RX_BW_40:
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if (mode & MT_PHY_TYPE_HE_EXT_SU &&
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(idx & MT_PRXV_TX_ER_SU_106T)) {
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status->bw = RATE_INFO_BW_HE_RU;
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status->he_ru =
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NL80211_RATE_INFO_HE_RU_ALLOC_106;
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} else {
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status->bw = RATE_INFO_BW_40;
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}
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break;
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case IEEE80211_STA_RX_BW_80:
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status->bw = RATE_INFO_BW_80;
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break;
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case IEEE80211_STA_RX_BW_160:
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status->bw = RATE_INFO_BW_160;
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break;
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default:
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return -EINVAL;
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}
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status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
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if (mode < MT_PHY_TYPE_HE_SU && gi)
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status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
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}
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}
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@ -97,18 +97,24 @@ enum rx_pkt_type {
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#define MT_RXD3_NORMAL_PF_MODE BIT(29)
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#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
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/* P-RXV */
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/* P-RXV DW0 */
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#define MT_PRXV_TX_RATE GENMASK(6, 0)
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#define MT_PRXV_TX_DCM BIT(4)
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#define MT_PRXV_TX_ER_SU_106T BIT(5)
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#define MT_PRXV_NSTS GENMASK(9, 7)
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#define MT_PRXV_HT_AD_CODE BIT(11)
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#define MT_PRXV_FRAME_MODE GENMASK(14, 12)
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#define MT_PRXV_SGI GENMASK(16, 15)
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#define MT_PRXV_STBC GENMASK(23, 22)
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#define MT_PRXV_TX_MODE GENMASK(27, 24)
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#define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
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#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
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/* P-RXV DW1 */
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#define MT_PRXV_RCPI3 GENMASK(31, 24)
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#define MT_PRXV_RCPI2 GENMASK(23, 16)
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#define MT_PRXV_RCPI1 GENMASK(15, 8)
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#define MT_PRXV_RCPI0 GENMASK(7, 0)
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#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
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/* C-RXV */
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#define MT_CRXV_HT_STBC GENMASK(1, 0)
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