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drm/i915/dp: Use auxch precharge value of 5 everywhere 

The default in the Sandybridge docs is 5, as on Ironlake, and I have no
reason to believe 3 would work any better.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Adam Jackson 2011-07-26 15:39:45 -04:00 committed by Daniel Vetter
parent 6919132e7a
commit 092945e11c
1 changed files with 1 additions and 6 deletions
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7
drivers/gpu/drm/i915/intel_dp.c
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@ -362,7 +362,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
int recv_bytes; int recv_bytes;
uint32_t status; uint32_t status;
uint32_t aux_clock_divider; uint32_t aux_clock_divider;
int try, precharge; int try, precharge = 5;
intel_dp_check_edp(intel_dp); intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk, /* The clock divider is based off the hrawclk,
@ -382,11 +382,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else else
aux_clock_divider = intel_hrawclk(dev) / 2; aux_clock_divider = intel_hrawclk(dev) / 2;
if (IS_GEN6(dev))
precharge = 3;
else
precharge = 5;
/* Try to wait for any previous AUX channel activity */ /* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) { for (try = 0; try < 3; try++) {
status = I915_READ(ch_ctl); status = I915_READ(ch_ctl);