powerpc/xmon: Apply binutils changes to upgrade disassembly
The following commit-ids from the binutils project were applied on the
xmon branch and relicensed with the permission of the authors under
GPLv2 for the following files:
ppc-opc.c
ppc-dis.c
ppc.h
Working off of binutils commit 65b650b4c746 we have now moved up to
binutils commit a5721ba270dd.
Some commit logs have been taken verbatim, some are summarized for ease
of understanding.
Here is a summary of the commits:
33e8d5ac613d PPC7450 New. (powerpc_opcodes): Use it in dcba.
c3d65c1ced61 New opcodes and mask
8dbcd839b1bb Instruction Sorting
91eb7075e370 (powerpc_opcodes): Fix the first two operands of dquaiq.
548b1dcfcbab ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix.
930bb4cfae30 Support optional L form mtmsr.
de866fccd87d (powerpc_opcodes): Order and format.
19a6653ce8c6 ppc e500mc support
fa452fa6833c (ppc_cpu_t): New typedef.
c8187e1509b2 (parse_cpu): Handle -m464.
081ba1b3c08b Define. (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI)
9b4e57660d38 Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7.
899d85beadd0 (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
e1c93c699b7d (extract_sprg): Correct operand range check.
2f3bb96af796 (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
1cb0a7674666 (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test
21169fcfadfa (print_insn_powerpc): Skip insn if it is deprecated
80890a619b85 ("dcbt", "dcbtst")
0e55be1624c2 ("lfdepx", "stfdepx")
066be9f7bd8e (parse_cpu): Extend -mpower7 to accept power7 and isel instructions.
c72ab5f2c55d (powerpc_opcodes): Reorder the opcode table so that instructions
69fe9ce501f5 (ppc_parse_cpu): New function. (powerpc_init_dialect)
e401b04ca7cd (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and E500MC entries.
70dc4e324b9a (powerpc_init_dialect): Do not choose a default dialect due to -many/-Many.
858d7a6db20b (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva", "tlbilx"
bdc7fcfe59f1 (powerpc_macros <extrdi>): Allow n+b of 64
e0d602ecffb0 (md_show_usage): Document -mpcca2
b961e85b6ebe (ppc_cpu_t): Typedef to uint64_t
8765b5569284 (powerpc_opcodes): Remove support for the the "lxsdux", "lxvd2ux"
634b50f2a623 Rename "ppca2" to "a2"
9fe54b1ca1c0 (md_show_usage): Document -m476
0dc9305793c8 Add bfd_mach_ppc_e500mc64
ce3d2015b21b Define. bfd/ * archures.c (bfd_mach_ppc_titan)
cdc51b0748c4 Add -mpwr4, -mpwr5, -mpwr5x, -mpwr6 and -mpwr7
63d0fa4e9e57 Add PPC_OPCODE_E500MC for "e500mc64"
cee62821d472 New Define. ("dccci"): Enable for PPCA2
85d4ac0b3c0b Correct wclr encoding.
51b5d4a8c5e5 (powerpc_opcodes): Enable divdeu, devweu, divde, divwe, divdeuo
e01d869a3be2 (md_assemble): Emit APUinfo section for PPC_OPCODE_E500
09a8ad8d8f56 (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf and mtocrf on EFS.
f2bae120dcef (PPC_OPCODE_COMMON): Expand comment.
81a0b7e2ae09 (PPCPWR2): Add PPC_OPCODE_COMMON. (powerpc_opcodes): Add "subc"
bdc70b4a03fd (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC)
7102e95e4943 (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting
f383de6633cb (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate on E500 and E500MC
6b069ee70de3 Remove PPC_OPCODE_PPCPS
2f7f77101279 (powerpc_opcodes): Enable icswx for POWER7
989993d80a97 (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX, RBX)
a08fc94222d1 <drrndq, drrndq., dtstexq, dctqpq, dctqpq., dctfixq, dctfixq.
8ebac3aae962 (ISA_V2): Define and use for relevant BO field tests
aea77599d0db Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR
b240011aba98 (disassemble_init_for_target): Handle ppc init.
d668828207c2 (powerpc_opcd_indices): Bump array size
b9c361e0ad33 Add support for PowerPC VLE.
e1dad58d73dc (has_tls_reloc, has_tls_get_addr_call, has_vle_insns, is_ppc_vle)
df7b86aa4cb6 Add check that sysdep.h has been included before
98c76446ea6b (extract_sprg): Use ALLOW8_SPRG to include VLE.
a4ebc835cbcb (powerpc_macros): Add entries for e_extlwi to e_clrlslwi
94caa966375d (has_vle_insns, is_ppc_vle): Delete
c7a8dbf91f37 Change RA to RA0
d908c8af5a1d Add necessary casts for printing integer values
03edbe3bfb93 Add/remove PPCVLE for some 32-bit insns
9f6a6cc022e1 <xnop, yield, mdoio, mdoom>: New extended mnemonics
588925d06545 <RSQ, RTQ>: Use PPC_OPERAND_GPR
8baf7b78b5d9 <"lswx">: Use RAX for the second and RBX for the third operand
e67ed0e885d6 Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt
fb048c26f19f (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK, VXVDVA_MASK
382c72e90441 (VXASHB_MASK): New define
c7a5aa9c64fc (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2
ab4437c3224f <vcfpsxws>: Fix opcode spelling
62082a42b9cd "lfdp" and "stfdp" use DS offset.
776fc41826bb (ppc_parse_cpu): Update prototype
943d398f4c52 (insert_sci8, extract_sci8): Rewrite.
5817ffd1f81c New define (PPC_OPCODE_HTM/POWER8)
9f0682fe89d9 (extract_vlesi): Properly sign extend
c0637f3af686 (powerpc_init_dialect): Set default dialect to power8.
58ae08f29af8 (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu
4f6ffcd38d90 (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect
4b95cf5c0c75 Update copyright years
a47622ac1bad Allow both signed and unsigned fields in PowerPC cmpli insn
12e87fac5c76 ppc: enable msgclr and msgsnd on Power8
8514e4db84cc Don't deprecate powerpc mftb insn
db76a70026ab Power4 should treat mftb as extended mfspr mnemonic
b90efa5b79ac ChangeLog rotatation and copyright year update
c4e676f19656 powerpc: Add slbfee. instruction
27c49e9a8fc0 powerpc: Only initialise opcode indices once
4fff86c517ab DCBT_EO): New define
4bc0608a8b69 Fix some PPC assembler errors
dc302c00611b Add hwsync extended mnemonic
99a2c5612124 Remove unused MTMSRD_L macro and re-add accidentally deleted comment
11a0cf2ec0ed Allow for optional operands with non-zero default values
7b9341139a69 PPC sync instruction accepts invalid and incompatible operands
ef5a96d564a2 Remove ppc860, ppc750cl, ppc7450 insns from common ppc
43e65147c07b Remove trailing spaces in opcodes
6dca4fd141fd Add dscr and ctrl SPR mnemonics
b6518b387185 Fix compile time warnings generated when compiling with clang
36f7a9411dcd Patches for illegal ppc 500 instructions
a680de9a980e Add assembler, disassembler and linker support for power9
dd2887fc3de4 Reorder some power9 insns
b817670b52b7 Enable 2 operand form of powerpc mfcr with -many
6f2750feaf28 Copyright update for binutils
afa8d4054b8e Delete opcodes that have been removed from ISA 3.0
1178da445ad5 Accept valid one byte signed and unsigned values for the IMM8 operand
e43de63c8fd1 Fix powerpc subis range
514e58b72633 Correct "Fix powerpc subis range"
19dfcc89e8d9 Add support for new POWER ISA 3.0 instructions
1fe0971e41a4 add more extern C
026122a67044 Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu
14b57c7c6a53 PowerPC VLE
6fd3a02da554 Add support for yet some more new ISA 3.0 instructions
dfdaec14b0db Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions
fd486b633e87 Modify POWER9 support to match final ISA 3.0 documentation
a5721ba270dd Disallow 3-operand cmp[l][i] for ppc64
This updates the disassembly capabilities to add support for newer
processors.
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
[mpe: Reformat commit list for brevity]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Balbir Singh
Michael Ellerman
parent
cc7639ce18
commit
08d96e0b12
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@ -1,6 +1,5 @@
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/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
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Free Software Foundation, Inc.
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Copyright (C) 1994-2016 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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@ -19,9 +18,12 @@ You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include <stdio.h>
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#include "dis-asm.h"
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#include "elf-bfd.h"
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#include "elf/ppc.h"
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#include "opintl.h"
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#include "opcode/ppc.h"
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/* This file provides several disassembler functions, all of which use
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@ -29,76 +31,380 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
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are provided because this file handles disassembly for the PowerPC
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in both big and little endian mode and also for the POWER (RS/6000)
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chip. */
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
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ppc_cpu_t);
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
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/* Determine which set of machines to disassemble for. PPC403/601 or
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BookE. For convenience, also disassemble instructions supported
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by the AltiVec vector unit. */
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static int
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powerpc_dialect (struct disassemble_info *info)
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struct dis_private
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{
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int dialect = PPC_OPCODE_PPC;
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/* Stash the result of parsing disassembler_options here. */
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ppc_cpu_t dialect;
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} private;
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if (BFD_DEFAULT_TARGET_SIZE == 64)
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dialect |= PPC_OPCODE_64;
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#define POWERPC_DIALECT(INFO) \
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(((struct dis_private *) ((INFO)->private_data))->dialect)
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "booke") != NULL)
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
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else if ((info->mach == bfd_mach_ppc_e500)
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|| (info->disassembler_options
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&& strstr (info->disassembler_options, "e500") != NULL))
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dialect |= (PPC_OPCODE_BOOKE
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| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
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| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_RFMCI);
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "efs") != NULL)
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dialect |= PPC_OPCODE_EFS;
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "e300") != NULL)
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dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "440") != NULL)
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
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| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
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struct ppc_mopt {
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const char *opt;
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ppc_cpu_t cpu;
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ppc_cpu_t sticky;
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};
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struct ppc_mopt ppc_opts[] = {
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{ "403", PPC_OPCODE_PPC | PPC_OPCODE_403,
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0 },
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{ "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
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0 },
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
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| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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0 },
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{ "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
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0 },
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{ "603", PPC_OPCODE_PPC,
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0 },
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{ "604", PPC_OPCODE_PPC,
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0 },
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{ "620", PPC_OPCODE_PPC | PPC_OPCODE_64,
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0 },
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{ "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
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0 },
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{ "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
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0 },
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{ "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
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, 0 },
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{ "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "860", PPC_OPCODE_PPC | PPC_OPCODE_860,
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0 },
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
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| PPC_OPCODE_A2),
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0 },
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{ "altivec", PPC_OPCODE_PPC,
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PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
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{ "any", 0,
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PPC_OPCODE_ANY },
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{ "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
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0 },
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{ "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
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0 },
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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0 },
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{ "com", PPC_OPCODE_COMMON,
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0 },
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{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
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PPC_OPCODE_VLE },
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{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
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0 },
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC),
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0 },
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{ "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7),
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0 },
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{ "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
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0 },
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{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500),
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0 },
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{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
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0 },
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{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
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0 },
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
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| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
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0 },
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{ "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
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| PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
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| PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
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0 },
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{ "ppc", PPC_OPCODE_PPC,
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0 },
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{ "ppc32", PPC_OPCODE_PPC,
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0 },
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{ "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64,
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0 },
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{ "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
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0 },
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{ "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
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0 },
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{ "pwr", PPC_OPCODE_POWER,
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0 },
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{ "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
|
||||
0 },
|
||||
{ "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
|
||||
0 },
|
||||
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5),
|
||||
0 },
|
||||
{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5),
|
||||
0 },
|
||||
{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
|
||||
0 },
|
||||
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
|
||||
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
|
||||
| PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
|
||||
| PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
|
||||
0 },
|
||||
{ "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
|
||||
0 },
|
||||
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
|
||||
PPC_OPCODE_SPE },
|
||||
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
|
||||
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
|
||||
0 },
|
||||
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
|
||||
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
|
||||
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
|
||||
| PPC_OPCODE_E500),
|
||||
PPC_OPCODE_VLE },
|
||||
{ "vsx", PPC_OPCODE_PPC,
|
||||
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
|
||||
{ "htm", PPC_OPCODE_PPC,
|
||||
PPC_OPCODE_HTM },
|
||||
};
|
||||
|
||||
/* Switch between Booke and VLE dialects for interlinked dumps. */
|
||||
static ppc_cpu_t
|
||||
get_powerpc_dialect (struct disassemble_info *info)
|
||||
{
|
||||
ppc_cpu_t dialect = 0;
|
||||
|
||||
dialect = POWERPC_DIALECT (info);
|
||||
|
||||
/* Disassemble according to the section headers flags for VLE-mode. */
|
||||
if (dialect & PPC_OPCODE_VLE
|
||||
&& info->section->owner != NULL
|
||||
&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
|
||||
&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
|
||||
&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
|
||||
return dialect;
|
||||
else
|
||||
dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
|
||||
| PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
|
||||
return dialect & ~ PPC_OPCODE_VLE;
|
||||
}
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "power4") != NULL)
|
||||
dialect |= PPC_OPCODE_POWER4;
|
||||
/* Handle -m and -M options that set cpu type, and .machine arg. */
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "power5") != NULL)
|
||||
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
|
||||
ppc_cpu_t
|
||||
ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "cell") != NULL)
|
||||
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
|
||||
for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
|
||||
if (strcmp (ppc_opts[i].opt, arg) == 0)
|
||||
{
|
||||
if (ppc_opts[i].sticky)
|
||||
{
|
||||
*sticky |= ppc_opts[i].sticky;
|
||||
if ((ppc_cpu & ~*sticky) != 0)
|
||||
break;
|
||||
}
|
||||
ppc_cpu = ppc_opts[i].cpu;
|
||||
break;
|
||||
}
|
||||
if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
|
||||
return 0;
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "power6") != NULL)
|
||||
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
|
||||
ppc_cpu |= *sticky;
|
||||
return ppc_cpu;
|
||||
}
|
||||
|
||||
if (info->disassembler_options
|
||||
&& strstr (info->disassembler_options, "any") != NULL)
|
||||
dialect |= PPC_OPCODE_ANY;
|
||||
/* Determine which set of machines to disassemble for. */
|
||||
|
||||
if (info->disassembler_options)
|
||||
static void
|
||||
powerpc_init_dialect (struct disassemble_info *info)
|
||||
{
|
||||
ppc_cpu_t dialect = 0;
|
||||
ppc_cpu_t sticky = 0;
|
||||
char *arg;
|
||||
struct dis_private *priv = calloc (sizeof (*priv), 1);
|
||||
|
||||
if (priv == NULL)
|
||||
priv = &private;
|
||||
|
||||
switch (info->mach)
|
||||
{
|
||||
if (strstr (info->disassembler_options, "32") != NULL)
|
||||
dialect &= ~PPC_OPCODE_64;
|
||||
else if (strstr (info->disassembler_options, "64") != NULL)
|
||||
dialect |= PPC_OPCODE_64;
|
||||
case bfd_mach_ppc_403:
|
||||
case bfd_mach_ppc_403gc:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "403");
|
||||
break;
|
||||
case bfd_mach_ppc_405:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "405");
|
||||
break;
|
||||
case bfd_mach_ppc_601:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "601");
|
||||
break;
|
||||
case bfd_mach_ppc_a35:
|
||||
case bfd_mach_ppc_rs64ii:
|
||||
case bfd_mach_ppc_rs64iii:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
|
||||
break;
|
||||
case bfd_mach_ppc_e500:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "e500");
|
||||
break;
|
||||
case bfd_mach_ppc_e500mc:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
|
||||
break;
|
||||
case bfd_mach_ppc_e500mc64:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
|
||||
break;
|
||||
case bfd_mach_ppc_e5500:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
|
||||
break;
|
||||
case bfd_mach_ppc_e6500:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
|
||||
break;
|
||||
case bfd_mach_ppc_titan:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "titan");
|
||||
break;
|
||||
case bfd_mach_ppc_vle:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "vle");
|
||||
break;
|
||||
default:
|
||||
dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
|
||||
}
|
||||
|
||||
info->private_data = (char *) 0 + dialect;
|
||||
return dialect;
|
||||
arg = info->disassembler_options;
|
||||
while (arg != NULL)
|
||||
{
|
||||
ppc_cpu_t new_cpu = 0;
|
||||
char *end = strchr (arg, ',');
|
||||
|
||||
if (end != NULL)
|
||||
*end = 0;
|
||||
|
||||
if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
|
||||
dialect = new_cpu;
|
||||
else if (strcmp (arg, "32") == 0)
|
||||
dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
|
||||
else if (strcmp (arg, "64") == 0)
|
||||
dialect |= PPC_OPCODE_64;
|
||||
else
|
||||
fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
|
||||
|
||||
if (end != NULL)
|
||||
*end++ = ',';
|
||||
arg = end;
|
||||
}
|
||||
|
||||
info->private_data = priv;
|
||||
POWERPC_DIALECT(info) = dialect;
|
||||
}
|
||||
|
||||
#define PPC_OPCD_SEGS 64
|
||||
static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
|
||||
#define VLE_OPCD_SEGS 32
|
||||
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
|
||||
|
||||
/* Calculate opcode table indices to speed up disassembly,
|
||||
and init dialect. */
|
||||
|
||||
void
|
||||
disassemble_init_powerpc (struct disassemble_info *info)
|
||||
{
|
||||
int i;
|
||||
unsigned short last;
|
||||
|
||||
if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
|
||||
{
|
||||
|
||||
i = powerpc_num_opcodes;
|
||||
while (--i >= 0)
|
||||
{
|
||||
unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
|
||||
|
||||
powerpc_opcd_indices[op] = i;
|
||||
}
|
||||
|
||||
last = powerpc_num_opcodes;
|
||||
for (i = PPC_OPCD_SEGS; i > 0; --i)
|
||||
{
|
||||
if (powerpc_opcd_indices[i] == 0)
|
||||
powerpc_opcd_indices[i] = last;
|
||||
last = powerpc_opcd_indices[i];
|
||||
}
|
||||
|
||||
i = vle_num_opcodes;
|
||||
while (--i >= 0)
|
||||
{
|
||||
unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
|
||||
unsigned seg = VLE_OP_TO_SEG (op);
|
||||
|
||||
vle_opcd_indices[seg] = i;
|
||||
}
|
||||
|
||||
last = vle_num_opcodes;
|
||||
for (i = VLE_OPCD_SEGS; i > 0; --i)
|
||||
{
|
||||
if (vle_opcd_indices[i] == 0)
|
||||
vle_opcd_indices[i] = last;
|
||||
last = vle_opcd_indices[i];
|
||||
}
|
||||
}
|
||||
|
||||
if (info->arch == bfd_arch_powerpc)
|
||||
powerpc_init_dialect (info);
|
||||
}
|
||||
|
||||
/* Print a big endian PowerPC instruction. */
|
||||
|
|
@ -106,8 +412,7 @@ powerpc_dialect (struct disassemble_info *info)
|
|||
int
|
||||
print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
int dialect = (char *) info->private_data - (char *) 0;
|
||||
return print_insn_powerpc (memaddr, info, 1, dialect);
|
||||
return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
|
||||
}
|
||||
|
||||
/* Print a little endian PowerPC instruction. */
|
||||
|
|
@ -115,8 +420,7 @@ print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
|||
int
|
||||
print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
int dialect = (char *) info->private_data - (char *) 0;
|
||||
return print_insn_powerpc (memaddr, info, 0, dialect);
|
||||
return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
|
||||
}
|
||||
|
||||
/* Print a POWER (RS/6000) instruction. */
|
||||
|
|
@ -131,7 +435,7 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
|
||||
static long
|
||||
operand_value_powerpc (const struct powerpc_operand *operand,
|
||||
unsigned long insn, int dialect)
|
||||
unsigned long insn, ppc_cpu_t dialect)
|
||||
{
|
||||
long value;
|
||||
int invalid;
|
||||
|
|
@ -140,11 +444,14 @@ operand_value_powerpc (const struct powerpc_operand *operand,
|
|||
value = (*operand->extract) (insn, dialect, &invalid);
|
||||
else
|
||||
{
|
||||
value = (insn >> operand->shift) & operand->bitm;
|
||||
if (operand->shift >= 0)
|
||||
value = (insn >> operand->shift) & operand->bitm;
|
||||
else
|
||||
value = (insn << -operand->shift) & operand->bitm;
|
||||
if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
|
||||
{
|
||||
/* BITM is always some number of zeros followed by some
|
||||
number of ones, followed by some numer of zeros. */
|
||||
number of ones, followed by some number of zeros. */
|
||||
unsigned long top = operand->bitm;
|
||||
/* top & -top gives the rightmost 1 bit, so this
|
||||
fills in any trailing zeros. */
|
||||
|
|
@ -161,7 +468,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,
|
|||
|
||||
static int
|
||||
skip_optional_operands (const unsigned char *opindex,
|
||||
unsigned long insn, int dialect)
|
||||
unsigned long insn, ppc_cpu_t dialect)
|
||||
{
|
||||
const struct powerpc_operand *operand;
|
||||
|
||||
|
|
@ -170,73 +477,44 @@ skip_optional_operands (const unsigned char *opindex,
|
|||
operand = &powerpc_operands[*opindex];
|
||||
if ((operand->flags & PPC_OPERAND_NEXT) != 0
|
||||
|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
||||
&& operand_value_powerpc (operand, insn, dialect) != 0))
|
||||
&& operand_value_powerpc (operand, insn, dialect) !=
|
||||
ppc_optional_operand_value (operand)))
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Print a PowerPC or POWER instruction. */
|
||||
/* Find a match for INSN in the opcode table, given machine DIALECT.
|
||||
A DIALECT of -1 is special, matching all machine opcode variations. */
|
||||
|
||||
static int
|
||||
print_insn_powerpc (bfd_vma memaddr,
|
||||
struct disassemble_info *info,
|
||||
int bigendian,
|
||||
int dialect)
|
||||
static const struct powerpc_opcode *
|
||||
lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
|
||||
{
|
||||
bfd_byte buffer[4];
|
||||
int status;
|
||||
unsigned long insn;
|
||||
const struct powerpc_opcode *opcode;
|
||||
const struct powerpc_opcode *opcode_end;
|
||||
unsigned long op;
|
||||
|
||||
if (dialect == 0)
|
||||
dialect = powerpc_dialect (info);
|
||||
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (bigendian)
|
||||
insn = bfd_getb32 (buffer);
|
||||
else
|
||||
insn = bfd_getl32 (buffer);
|
||||
|
||||
/* Get the major opcode of the instruction. */
|
||||
op = PPC_OP (insn);
|
||||
|
||||
/* Find the first match in the opcode table. We could speed this up
|
||||
a bit by doing a binary search on the major opcode. */
|
||||
opcode_end = powerpc_opcodes + powerpc_num_opcodes;
|
||||
again:
|
||||
for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
|
||||
/* Find the first match in the opcode table for this major opcode. */
|
||||
opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
|
||||
for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
|
||||
opcode < opcode_end;
|
||||
++opcode)
|
||||
{
|
||||
unsigned long table_op;
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int invalid;
|
||||
int need_comma;
|
||||
int need_paren;
|
||||
int skip_optional;
|
||||
|
||||
table_op = PPC_OP (opcode->opcode);
|
||||
if (op < table_op)
|
||||
break;
|
||||
if (op > table_op)
|
||||
continue;
|
||||
|
||||
if ((insn & opcode->mask) != opcode->opcode
|
||||
|| (opcode->flags & dialect) == 0)
|
||||
|| (dialect != (ppc_cpu_t) -1
|
||||
&& ((opcode->flags & dialect) == 0
|
||||
|| (opcode->deprecated & dialect) != 0)))
|
||||
continue;
|
||||
|
||||
/* Make two passes over the operands. First see if any of them
|
||||
have extraction functions, and, if they do, make sure the
|
||||
instruction is valid. */
|
||||
/* Check validity of operands. */
|
||||
invalid = 0;
|
||||
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
||||
{
|
||||
|
|
@ -247,12 +525,138 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
if (invalid)
|
||||
continue;
|
||||
|
||||
/* The instruction is valid. */
|
||||
return opcode;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Find a match for INSN in the VLE opcode table. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
lookup_vle (unsigned long insn)
|
||||
{
|
||||
const struct powerpc_opcode *opcode;
|
||||
const struct powerpc_opcode *opcode_end;
|
||||
unsigned op, seg;
|
||||
|
||||
op = PPC_OP (insn);
|
||||
if (op >= 0x20 && op <= 0x37)
|
||||
{
|
||||
/* This insn has a 4-bit opcode. */
|
||||
op &= 0x3c;
|
||||
}
|
||||
seg = VLE_OP_TO_SEG (op);
|
||||
|
||||
/* Find the first match in the opcode table for this major opcode. */
|
||||
opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
|
||||
for (opcode = vle_opcodes + vle_opcd_indices[seg];
|
||||
opcode < opcode_end;
|
||||
++opcode)
|
||||
{
|
||||
unsigned long table_opcd = opcode->opcode;
|
||||
unsigned long table_mask = opcode->mask;
|
||||
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
|
||||
unsigned long insn2;
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int invalid;
|
||||
|
||||
insn2 = insn;
|
||||
if (table_op_is_short)
|
||||
insn2 >>= 16;
|
||||
if ((insn2 & table_mask) != table_opcd)
|
||||
continue;
|
||||
|
||||
/* Check validity of operands. */
|
||||
invalid = 0;
|
||||
for (opindex = opcode->operands; *opindex != 0; ++opindex)
|
||||
{
|
||||
operand = powerpc_operands + *opindex;
|
||||
if (operand->extract)
|
||||
(*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
|
||||
}
|
||||
if (invalid)
|
||||
continue;
|
||||
|
||||
return opcode;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Print a PowerPC or POWER instruction. */
|
||||
|
||||
static int
|
||||
print_insn_powerpc (bfd_vma memaddr,
|
||||
struct disassemble_info *info,
|
||||
int bigendian,
|
||||
ppc_cpu_t dialect)
|
||||
{
|
||||
bfd_byte buffer[4];
|
||||
int status;
|
||||
unsigned long insn;
|
||||
const struct powerpc_opcode *opcode;
|
||||
bfd_boolean insn_is_short;
|
||||
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
|
||||
if (status != 0)
|
||||
{
|
||||
/* The final instruction may be a 2-byte VLE insn. */
|
||||
if ((dialect & PPC_OPCODE_VLE) != 0)
|
||||
{
|
||||
/* Clear buffer so unused bytes will not have garbage in them. */
|
||||
buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
|
||||
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (bigendian)
|
||||
insn = bfd_getb32 (buffer);
|
||||
else
|
||||
insn = bfd_getl32 (buffer);
|
||||
|
||||
/* Get the major opcode of the insn. */
|
||||
opcode = NULL;
|
||||
insn_is_short = FALSE;
|
||||
if ((dialect & PPC_OPCODE_VLE) != 0)
|
||||
{
|
||||
opcode = lookup_vle (insn);
|
||||
if (opcode != NULL)
|
||||
insn_is_short = PPC_OP_SE_VLE(opcode->mask);
|
||||
}
|
||||
if (opcode == NULL)
|
||||
opcode = lookup_powerpc (insn, dialect);
|
||||
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
|
||||
opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
|
||||
|
||||
if (opcode != NULL)
|
||||
{
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int need_comma;
|
||||
int need_paren;
|
||||
int skip_optional;
|
||||
|
||||
if (opcode->operands[0] != 0)
|
||||
(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
||||
|
||||
if (insn_is_short)
|
||||
/* The operands will be fetched out of the 16-bit instruction. */
|
||||
insn >>= 16;
|
||||
|
||||
/* Now extract and print the operands. */
|
||||
need_comma = 0;
|
||||
need_paren = 0;
|
||||
|
|
@ -296,30 +700,38 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
(*info->fprintf_func) (info->stream, "f%ld", value);
|
||||
else if ((operand->flags & PPC_OPERAND_VR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "v%ld", value);
|
||||
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "vs%ld", value);
|
||||
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
|
||||
(*info->print_address_func) (memaddr + value, info);
|
||||
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
|
||||
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
|
||||
else if ((operand->flags & PPC_OPERAND_CR) == 0
|
||||
|| (dialect & PPC_OPCODE_PPC) == 0)
|
||||
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
|
||||
(*info->fprintf_func) (info->stream, "fsl%ld", value);
|
||||
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
|
||||
(*info->fprintf_func) (info->stream, "fcr%ld", value);
|
||||
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
|
||||
(*info->fprintf_func) (info->stream, "%ld", value);
|
||||
else
|
||||
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
|
||||
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
||||
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
||||
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
||||
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
|
||||
&& (((dialect & PPC_OPCODE_PPC) != 0)
|
||||
|| ((dialect & PPC_OPCODE_VLE) != 0)))
|
||||
{
|
||||
if (operand->bitm == 7)
|
||||
(*info->fprintf_func) (info->stream, "cr%ld", value);
|
||||
else
|
||||
{
|
||||
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
||||
int cr;
|
||||
int cc;
|
||||
static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
|
||||
int cr;
|
||||
int cc;
|
||||
|
||||
cr = value >> 2;
|
||||
if (cr != 0)
|
||||
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
||||
cc = value & 3;
|
||||
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
||||
}
|
||||
cr = value >> 2;
|
||||
if (cr != 0)
|
||||
(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
|
||||
cc = value & 3;
|
||||
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%d", (int) value);
|
||||
|
||||
if (need_paren)
|
||||
{
|
||||
|
|
@ -336,14 +748,16 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
}
|
||||
}
|
||||
|
||||
/* We have found and printed an instruction; return. */
|
||||
return 4;
|
||||
}
|
||||
|
||||
if ((dialect & PPC_OPCODE_ANY) != 0)
|
||||
{
|
||||
dialect = ~PPC_OPCODE_ANY;
|
||||
goto again;
|
||||
/* We have found and printed an instruction.
|
||||
If it was a short VLE instruction we have more to do. */
|
||||
if (insn_is_short)
|
||||
{
|
||||
memaddr += 2;
|
||||
return 2;
|
||||
}
|
||||
else
|
||||
/* Otherwise, return. */
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* We could not find a match. */
|
||||
|
|
@ -355,18 +769,20 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
void
|
||||
print_ppc_disassembler_options (FILE *stream)
|
||||
{
|
||||
fprintf (stream, "\n\
|
||||
The following PPC specific disassembler options are supported for use with\n\
|
||||
the -M switch:\n");
|
||||
unsigned int i, col;
|
||||
|
||||
fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n");
|
||||
fprintf (stream, " e300 Disassemble the e300 instructions\n");
|
||||
fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
|
||||
fprintf (stream, " 440 Disassemble the 440 instructions\n");
|
||||
fprintf (stream, " efs Disassemble the EFS instructions\n");
|
||||
fprintf (stream, " power4 Disassemble the Power4 instructions\n");
|
||||
fprintf (stream, " power5 Disassemble the Power5 instructions\n");
|
||||
fprintf (stream, " power6 Disassemble the Power6 instructions\n");
|
||||
fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
|
||||
fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
|
||||
fprintf (stream, _("\n\
|
||||
The following PPC specific disassembler options are supported for use with\n\
|
||||
the -M switch:\n"));
|
||||
|
||||
for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
|
||||
{
|
||||
col += fprintf (stream, " %s,", ppc_opts[i].opt);
|
||||
if (col > 66)
|
||||
{
|
||||
fprintf (stream, "\n");
|
||||
col = 0;
|
||||
}
|
||||
}
|
||||
fprintf (stream, " 32, 64\n");
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,5 @@
|
|||
/* ppc.h -- Header file for PowerPC opcode table
|
||||
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
|
||||
2007 Free Software Foundation, Inc.
|
||||
Copyright (C) 1994-2016 Free Software Foundation, Inc.
|
||||
Written by Ian Lance Taylor, Cygnus Support
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
|
@ -22,6 +21,14 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
|
|||
#ifndef PPC_H
|
||||
#define PPC_H
|
||||
|
||||
#include "bfd_stdint.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef uint64_t ppc_cpu_t;
|
||||
|
||||
/* The opcode table is an array of struct powerpc_opcode. */
|
||||
|
||||
struct powerpc_opcode
|
||||
|
|
@ -42,7 +49,12 @@ struct powerpc_opcode
|
|||
/* One bit flags for the opcode. These are used to indicate which
|
||||
specific processors support the instructions. The defined values
|
||||
are listed below. */
|
||||
unsigned long flags;
|
||||
ppc_cpu_t flags;
|
||||
|
||||
/* One bit flags for the opcode. These are used to indicate which
|
||||
specific processors no longer support the instructions. The defined
|
||||
values are listed below. */
|
||||
ppc_cpu_t deprecated;
|
||||
|
||||
/* An array of operand codes. Each code is an index into the
|
||||
operand table. They appear in the order which the operands must
|
||||
|
|
@ -55,6 +67,8 @@ struct powerpc_opcode
|
|||
instructions. */
|
||||
extern const struct powerpc_opcode powerpc_opcodes[];
|
||||
extern const int powerpc_num_opcodes;
|
||||
extern const struct powerpc_opcode vle_opcodes[];
|
||||
extern const int vle_num_opcodes;
|
||||
|
||||
/* Values defined for the flags field of a struct powerpc_opcode. */
|
||||
|
||||
|
|
@ -67,87 +81,152 @@ extern const int powerpc_num_opcodes;
|
|||
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
|
||||
#define PPC_OPCODE_POWER2 4
|
||||
|
||||
/* Opcode is only defined on 32 bit architectures. */
|
||||
#define PPC_OPCODE_32 8
|
||||
|
||||
/* Opcode is only defined on 64 bit architectures. */
|
||||
#define PPC_OPCODE_64 0x10
|
||||
|
||||
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
|
||||
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
|
||||
but it also supports many additional POWER instructions. */
|
||||
#define PPC_OPCODE_601 0x20
|
||||
#define PPC_OPCODE_601 8
|
||||
|
||||
/* Opcode is supported in both the Power and PowerPC architectures
|
||||
(ie, compiler's -mcpu=common or assembler's -mcom). */
|
||||
#define PPC_OPCODE_COMMON 0x40
|
||||
(ie, compiler's -mcpu=common or assembler's -mcom). More than just
|
||||
the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
|
||||
and PPC_OPCODE_POWER2 because many instructions changed mnemonics
|
||||
between POWER and POWERPC. */
|
||||
#define PPC_OPCODE_COMMON 0x10
|
||||
|
||||
/* Opcode is supported for any Power or PowerPC platform (this is
|
||||
for the assembler's -many option, and it eliminates duplicates). */
|
||||
#define PPC_OPCODE_ANY 0x80
|
||||
#define PPC_OPCODE_ANY 0x20
|
||||
|
||||
/* Opcode is only defined on 64 bit architectures. */
|
||||
#define PPC_OPCODE_64 0x40
|
||||
|
||||
/* Opcode is supported as part of the 64-bit bridge. */
|
||||
#define PPC_OPCODE_64_BRIDGE 0x100
|
||||
#define PPC_OPCODE_64_BRIDGE 0x80
|
||||
|
||||
/* Opcode is supported by Altivec Vector Unit */
|
||||
#define PPC_OPCODE_ALTIVEC 0x200
|
||||
#define PPC_OPCODE_ALTIVEC 0x100
|
||||
|
||||
/* Opcode is supported by PowerPC 403 processor. */
|
||||
#define PPC_OPCODE_403 0x400
|
||||
#define PPC_OPCODE_403 0x200
|
||||
|
||||
/* Opcode is supported by PowerPC BookE processor. */
|
||||
#define PPC_OPCODE_BOOKE 0x800
|
||||
|
||||
/* Opcode is only supported by 64-bit PowerPC BookE processor. */
|
||||
#define PPC_OPCODE_BOOKE64 0x1000
|
||||
#define PPC_OPCODE_BOOKE 0x400
|
||||
|
||||
/* Opcode is supported by PowerPC 440 processor. */
|
||||
#define PPC_OPCODE_440 0x2000
|
||||
#define PPC_OPCODE_440 0x800
|
||||
|
||||
/* Opcode is only supported by Power4 architecture. */
|
||||
#define PPC_OPCODE_POWER4 0x4000
|
||||
#define PPC_OPCODE_POWER4 0x1000
|
||||
|
||||
/* Opcode isn't supported by Power4 architecture. */
|
||||
#define PPC_OPCODE_NOPOWER4 0x8000
|
||||
|
||||
/* Opcode is only supported by POWERPC Classic architecture. */
|
||||
#define PPC_OPCODE_CLASSIC 0x10000
|
||||
/* Opcode is only supported by Power7 architecture. */
|
||||
#define PPC_OPCODE_POWER7 0x2000
|
||||
|
||||
/* Opcode is only supported by e500x2 Core. */
|
||||
#define PPC_OPCODE_SPE 0x20000
|
||||
#define PPC_OPCODE_SPE 0x4000
|
||||
|
||||
/* Opcode is supported by e500x2 Integer select APU. */
|
||||
#define PPC_OPCODE_ISEL 0x40000
|
||||
#define PPC_OPCODE_ISEL 0x8000
|
||||
|
||||
/* Opcode is an e500 SPE floating point instruction. */
|
||||
#define PPC_OPCODE_EFS 0x80000
|
||||
#define PPC_OPCODE_EFS 0x10000
|
||||
|
||||
/* Opcode is supported by branch locking APU. */
|
||||
#define PPC_OPCODE_BRLOCK 0x100000
|
||||
#define PPC_OPCODE_BRLOCK 0x20000
|
||||
|
||||
/* Opcode is supported by performance monitor APU. */
|
||||
#define PPC_OPCODE_PMR 0x200000
|
||||
#define PPC_OPCODE_PMR 0x40000
|
||||
|
||||
/* Opcode is supported by cache locking APU. */
|
||||
#define PPC_OPCODE_CACHELCK 0x400000
|
||||
#define PPC_OPCODE_CACHELCK 0x80000
|
||||
|
||||
/* Opcode is supported by machine check APU. */
|
||||
#define PPC_OPCODE_RFMCI 0x800000
|
||||
#define PPC_OPCODE_RFMCI 0x100000
|
||||
|
||||
/* Opcode is only supported by Power5 architecture. */
|
||||
#define PPC_OPCODE_POWER5 0x1000000
|
||||
#define PPC_OPCODE_POWER5 0x200000
|
||||
|
||||
/* Opcode is supported by PowerPC e300 family. */
|
||||
#define PPC_OPCODE_E300 0x2000000
|
||||
#define PPC_OPCODE_E300 0x400000
|
||||
|
||||
/* Opcode is only supported by Power6 architecture. */
|
||||
#define PPC_OPCODE_POWER6 0x4000000
|
||||
#define PPC_OPCODE_POWER6 0x800000
|
||||
|
||||
/* Opcode is only supported by PowerPC Cell family. */
|
||||
#define PPC_OPCODE_CELL 0x8000000
|
||||
#define PPC_OPCODE_CELL 0x1000000
|
||||
|
||||
/* Opcode is supported by CPUs with paired singles support. */
|
||||
#define PPC_OPCODE_PPCPS 0x2000000
|
||||
|
||||
/* Opcode is supported by Power E500MC */
|
||||
#define PPC_OPCODE_E500MC 0x4000000
|
||||
|
||||
/* Opcode is supported by PowerPC 405 processor. */
|
||||
#define PPC_OPCODE_405 0x8000000
|
||||
|
||||
/* Opcode is supported by Vector-Scalar (VSX) Unit */
|
||||
#define PPC_OPCODE_VSX 0x10000000
|
||||
|
||||
/* Opcode is supported by A2. */
|
||||
#define PPC_OPCODE_A2 0x20000000
|
||||
|
||||
/* Opcode is supported by PowerPC 476 processor. */
|
||||
#define PPC_OPCODE_476 0x40000000
|
||||
|
||||
/* Opcode is supported by AppliedMicro Titan core */
|
||||
#define PPC_OPCODE_TITAN 0x80000000
|
||||
|
||||
/* Opcode which is supported by the e500 family */
|
||||
#define PPC_OPCODE_E500 0x100000000ull
|
||||
|
||||
/* Opcode is supported by Extended Altivec Vector Unit */
|
||||
#define PPC_OPCODE_ALTIVEC2 0x200000000ull
|
||||
|
||||
/* Opcode is supported by Power E6500 */
|
||||
#define PPC_OPCODE_E6500 0x400000000ull
|
||||
|
||||
/* Opcode is supported by Thread management APU */
|
||||
#define PPC_OPCODE_TMR 0x800000000ull
|
||||
|
||||
/* Opcode which is supported by the VLE extension. */
|
||||
#define PPC_OPCODE_VLE 0x1000000000ull
|
||||
|
||||
/* Opcode is only supported by Power8 architecture. */
|
||||
#define PPC_OPCODE_POWER8 0x2000000000ull
|
||||
|
||||
/* Opcode which is supported by the Hardware Transactional Memory extension. */
|
||||
/* Currently, this is the same as the POWER8 mask. If another cpu comes out
|
||||
that isn't a superset of POWER8, we can define this to its own mask. */
|
||||
#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
|
||||
|
||||
/* Opcode is supported by ppc750cl. */
|
||||
#define PPC_OPCODE_750 0x4000000000ull
|
||||
|
||||
/* Opcode is supported by ppc7450. */
|
||||
#define PPC_OPCODE_7450 0x8000000000ull
|
||||
|
||||
/* Opcode is supported by ppc821/850/860. */
|
||||
#define PPC_OPCODE_860 0x10000000000ull
|
||||
|
||||
/* Opcode is only supported by Power9 architecture. */
|
||||
#define PPC_OPCODE_POWER9 0x20000000000ull
|
||||
|
||||
/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
|
||||
#define PPC_OPCODE_VSX3 0x40000000000ull
|
||||
|
||||
/* Opcode is supported by e200z4. */
|
||||
#define PPC_OPCODE_E200Z4 0x80000000000ull
|
||||
|
||||
/* A macro to extract the major opcode from an instruction. */
|
||||
#define PPC_OP(i) (((i) >> 26) & 0x3f)
|
||||
|
||||
/* A macro to determine if the instruction is a 2-byte VLE insn. */
|
||||
#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
|
||||
|
||||
/* A macro to extract the major opcode from a VLE instruction. */
|
||||
#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
|
||||
|
||||
/* A macro to convert a VLE opcode to a VLE opcode segment. */
|
||||
#define VLE_OP_TO_SEG(i) ((i) >> 1)
|
||||
|
||||
/* The operands table is an array of struct powerpc_operand. */
|
||||
|
||||
|
|
@ -156,16 +235,22 @@ struct powerpc_operand
|
|||
/* A bitmask of bits in the operand. */
|
||||
unsigned int bitm;
|
||||
|
||||
/* How far the operand is left shifted in the instruction.
|
||||
-1 to indicate that BITM and SHIFT cannot be used to determine
|
||||
where the operand goes in the insn. */
|
||||
/* The shift operation to be applied to the operand. No shift
|
||||
is made if this is zero. For positive values, the operand
|
||||
is shifted left by SHIFT. For negative values, the operand
|
||||
is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
|
||||
that BITM and SHIFT cannot be used to determine where the
|
||||
operand goes in the insn. */
|
||||
int shift;
|
||||
|
||||
/* Insertion function. This is used by the assembler. To insert an
|
||||
operand value into an instruction, check this field.
|
||||
|
||||
If it is NULL, execute
|
||||
i |= (op & o->bitm) << o->shift;
|
||||
if (o->shift >= 0)
|
||||
i |= (op & o->bitm) << o->shift;
|
||||
else
|
||||
i |= (op & o->bitm) >> -o->shift;
|
||||
(i is the instruction which we are filling in, o is a pointer to
|
||||
this structure, and op is the operand value).
|
||||
|
||||
|
|
@ -177,13 +262,16 @@ struct powerpc_operand
|
|||
operand value is legal, *ERRMSG will be unchanged (most operands
|
||||
can accept any value). */
|
||||
unsigned long (*insert)
|
||||
(unsigned long instruction, long op, int dialect, const char **errmsg);
|
||||
(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
|
||||
|
||||
/* Extraction function. This is used by the disassembler. To
|
||||
extract this operand type from an instruction, check this field.
|
||||
|
||||
If it is NULL, compute
|
||||
op = (i >> o->shift) & o->bitm;
|
||||
if (o->shift >= 0)
|
||||
op = (i >> o->shift) & o->bitm;
|
||||
else
|
||||
op = (i << -o->shift) & o->bitm;
|
||||
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
|
||||
sign_extend (op);
|
||||
(i is the instruction, o is a pointer to this structure, and op
|
||||
|
|
@ -195,7 +283,7 @@ struct powerpc_operand
|
|||
non-zero if this operand type can not actually be extracted from
|
||||
this operand (i.e., the instruction does not match). If the
|
||||
operand is valid, *INVALID will not be changed. */
|
||||
long (*extract) (unsigned long instruction, int dialect, int *invalid);
|
||||
long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
|
||||
|
||||
/* One bit syntax flags. */
|
||||
unsigned long flags;
|
||||
|
|
@ -207,6 +295,11 @@ struct powerpc_operand
|
|||
extern const struct powerpc_operand powerpc_operands[];
|
||||
extern const unsigned int num_powerpc_operands;
|
||||
|
||||
/* Use with the shift field of a struct powerpc_operand to indicate
|
||||
that BITM and SHIFT cannot be used to determine where the operand
|
||||
goes in the insn. */
|
||||
#define PPC_OPSHIFT_INV (-1U << 31)
|
||||
|
||||
/* Values defined for the flags field of a struct powerpc_operand. */
|
||||
|
||||
/* This operand takes signed values. */
|
||||
|
|
@ -240,7 +333,7 @@ extern const unsigned int num_powerpc_operands;
|
|||
cr4 4 cr5 5 cr6 6 cr7 7
|
||||
These may be combined arithmetically, as in cr2*4+gt. These are
|
||||
only supported on the PowerPC, not the POWER. */
|
||||
#define PPC_OPERAND_CR (0x10)
|
||||
#define PPC_OPERAND_CR_BIT (0x10)
|
||||
|
||||
/* This operand names a register. The disassembler uses this to print
|
||||
register names with a leading 'r'. */
|
||||
|
|
@ -296,6 +389,27 @@ extern const unsigned int num_powerpc_operands;
|
|||
|
||||
/* Valid range of operand is 0..n rather than 0..n-1. */
|
||||
#define PPC_OPERAND_PLUS1 (0x10000)
|
||||
|
||||
/* Xilinx APU and FSL related operands */
|
||||
#define PPC_OPERAND_FSL (0x20000)
|
||||
#define PPC_OPERAND_FCR (0x40000)
|
||||
#define PPC_OPERAND_UDI (0x80000)
|
||||
|
||||
/* This operand names a vector-scalar unit register. The disassembler
|
||||
prints these with a leading 'vs'. */
|
||||
#define PPC_OPERAND_VSR (0x100000)
|
||||
|
||||
/* This is a CR FIELD that does not use symbolic names. */
|
||||
#define PPC_OPERAND_CR_REG (0x200000)
|
||||
|
||||
/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
|
||||
is omitted, then the value it should use for the operand is stored
|
||||
in the SHIFT field of the immediatly following operand field. */
|
||||
#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
|
||||
|
||||
/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
|
||||
only optional when generating 32-bit code. */
|
||||
#define PPC_OPERAND_OPTIONAL32 (0x800000)
|
||||
|
||||
/* The POWER and PowerPC assemblers use a few macros. We keep them
|
||||
with the operands table for simplicity. The macro table is an
|
||||
|
|
@ -312,7 +426,7 @@ struct powerpc_macro
|
|||
/* One bit flags for the opcode. These are used to indicate which
|
||||
specific processors support the instructions. The values are the
|
||||
same as those for the struct powerpc_opcode flags field. */
|
||||
unsigned long flags;
|
||||
ppc_cpu_t flags;
|
||||
|
||||
/* A format string to turn the macro into a normal instruction.
|
||||
Each %N in the string is replaced with operand number N (zero
|
||||
|
|
@ -323,4 +437,18 @@ struct powerpc_macro
|
|||
extern const struct powerpc_macro powerpc_macros[];
|
||||
extern const int powerpc_num_macros;
|
||||
|
||||
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
|
||||
|
||||
static inline long
|
||||
ppc_optional_operand_value (const struct powerpc_operand *operand)
|
||||
{
|
||||
if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
|
||||
return (operand+1)->shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PPC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue