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mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits 

In case if quotient of controller clock rate to device clock rate does
not fit into 4 bit value, choose the maximum acceptable value 0xF, which
stands for 16 clocks.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Vladimir Zapolskiy 2015-10-01 02:23:36 +03:00 committed by Brian Norris
parent 641f6342f5
commit 08d3cd5ef0
1 changed files with 1 additions and 1 deletions
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2
drivers/mtd/nand/lpc32xx_slc.c
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@ -95,7 +95,7 @@
* slc_tac register definitions * slc_tac register definitions
**********************************************************************/ **********************************************************************/
/* Computation of clock cycles on basis of controller and device clock rates */ /* Computation of clock cycles on basis of controller and device clock rates */
#define SLCTAC_CLOCKS(c, n, s) (((1 + (c / n)) & 0xF) << s) #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s)
/* Clock setting for RDY write sample wait time in 2*n clocks */ /* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28) #define SLCTAC_WDR(n) (((n) & 0xF) << 28)