From 07fb85a386a8444178a2f64a97260d39b8b8992b Mon Sep 17 00:00:00 2001 From: Chen Zhuo Date: Tue, 4 Jan 2022 20:43:29 +0800 Subject: [PATCH] Enumerate AVX Vector Neural Network instructions commit b85a0425d8056f3bd8d0a94ecdddf2a39d32a801 upstream. Add AVX version of the Vector Neural Network (VNNI) Instructions. A processor supports AVX VNNI instructions if CPUID.0x07.0x1:EAX[4] is present. The following instructions are available when this feature is present. 1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes 2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation 3. VPDPWSSD: Multiply and Add Signed Word Integers 4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation The only in-kernel usage of this is kvm passthrough. The CPU feature flag is shown as "avx_vnni" in /proc/cpuinfo. This instruction is currently documented in the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park Signed-off-by: Yang Zhong Reviewed-by: Tony Luck Message-Id: <20210105004909.42000-2-yang.zhong@intel.com> Acked-by: Borislav Petkov Signed-off-by: Paolo Bonzini Signed-off-by: Chen Zhuo Signed-off-by: Xinghui Li --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 1bf62f7fd480..ae1dbfcbd5cb 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -288,6 +288,7 @@ #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ +#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */