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staging: r8188eu: RFType type is always ODM_1T1R 

This driver is for 1T1R chips. The field RfType of odm_dm_struct is
set to ODM_1T1R and never changed. Remove code that initializes RFType,
remove it from odm_dm_struct and remove resulting dead code.

Acked-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Michael Straube <straube.linux@gmail.com>
Link: https://lore.kernel.org/r/20211019135137.9893-8-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Michael Straube 2021-10-19 15:51:37 +02:00 committed by Greg Kroah-Hartman
parent b7a96e0d40
commit 07e00148a2
4 changed files with 14 additions and 129 deletions
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82
drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
View File

@ -583,50 +583,6 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u
}
}
static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u8 final_candidate, bool txonly)
{
u32 Oldval_1, X, TX1_A, reg;
s32 Y, TX1_C;
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
if (final_candidate == 0xFF) {
return;
} else if (iqkok) {
Oldval_1 = (ODM_GetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
X = result[final_candidate][4];
if ((X & 0x00000200) != 0)
X = X | 0xFFFFFC00;
TX1_A = (X * Oldval_1) >> 8;
ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1));
Y = result[final_candidate][5];
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
TX1_C = (Y * Oldval_1) >> 8;
ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6));
ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F));
ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1));
if (txonly)
return;
reg = result[final_candidate][6];
ODM_SetBBReg(dm_odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
reg = result[final_candidate][7] & 0x3F;
ODM_SetBBReg(dm_odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
reg = (result[final_candidate][7] >> 6) & 0xF;
ODM_SetBBReg(dm_odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);
}
}
void _PHY_SaveADDARegisters(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum)
{
u32 i;
@ -759,23 +715,11 @@ static bool phy_SimularityCompare_8188E(
)
{
u32 i, j, diff, sim_bitmap, bound = 0;
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
bool result = true;
bool is2t;
s32 tmp1 = 0, tmp2 = 0;
if ((dm_odm->RFType == ODM_2T2R) || (dm_odm->RFType == ODM_2T3R) || (dm_odm->RFType == ODM_2T4R))
is2t = true;
else
is2t = false;
if (is2t)
bound = 8;
else
bound = 4;
bound = 4;
sim_bitmap = 0;
for (i = 0; i < bound; i++) {
@ -1049,8 +993,8 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
s32 result[4][8]; /* last is final result */
u8 i, final_candidate;
bool pathaok, pathbok;
s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC, RegEC4;
bool pathaok;
s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC;
bool is12simular, is13simular, is23simular;
bool singletone = false, carrier_sup = false;
u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
@ -1059,9 +1003,6 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
rOFDM0_RxIQExtAnta};
bool is2t;
is2t = (dm_odm->RFType == ODM_2T2R) ? true : false;
if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
return;
@ -1086,13 +1027,12 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
}
final_candidate = 0xff;
pathaok = false;
pathbok = false;
is12simular = false;
is23simular = false;
is13simular = false;
for (i = 0; i < 3; i++) {
phy_IQCalibrate_8188E(adapt, result, i, is2t);
phy_IQCalibrate_8188E(adapt, result, i, false);
if (i == 1) {
is12simular = phy_SimularityCompare_8188E(adapt, result, 0, 1);
@ -1124,7 +1064,6 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
RegEA4 = result[i][2];
RegEB4 = result[i][4];
RegEBC = result[i][5];
RegEC4 = result[i][6];
}
if (final_candidate != 0xff) {
@ -1137,9 +1076,7 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
dm_odm->RFCalibrateInfo.RegE9C = RegE9C;
dm_odm->RFCalibrateInfo.RegEB4 = RegEB4;
dm_odm->RFCalibrateInfo.RegEBC = RegEBC;
RegEC4 = result[final_candidate][6];
pathaok = true;
pathbok = true;
} else {
dm_odm->RFCalibrateInfo.RegE94 = 0x100;
dm_odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */
@ -1148,10 +1085,6 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
}
if (RegE94 != 0)
patha_fill_iqk(adapt, pathaok, result, final_candidate, (RegEA4 == 0));
if (is2t) {
if (RegEB4 != 0)
pathb_fill_iqk(adapt, pathbok, result, final_candidate, (RegEC4 == 0));
}
/* To Fix BSOD when final_candidate is 0xff */
/* by sherry 20120321 */
@ -1182,10 +1115,5 @@ void PHY_LCCalibrate_8188E(struct adapter *adapt)
timecount += 50;
}
if (dm_odm->RFType == ODM_2T2R) {
phy_LCCalibrate_8188E(adapt, true);
} else {
/* For 88C 1T1R */
phy_LCCalibrate_8188E(adapt, false);
}
phy_LCCalibrate_8188E(adapt, false);
}

40
drivers/staging/r8188eu/hal/odm.c
View File

@ -202,9 +202,6 @@ void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def Cmn
case ODM_CMNINFO_MP_TEST_CHIP:
pDM_Odm->bIsMPChip = (u8)Value;
break;
case ODM_CMNINFO_RF_TYPE:
pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_RF_ANTENNA_TYPE:
pDM_Odm->AntDivType = (u8)Value;
break;
@ -275,9 +272,6 @@ void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value)
case ODM_CMNINFO_ABILITY:
pDM_Odm->SupportAbility = (u32)Value;
break;
case ODM_CMNINFO_RF_TYPE:
pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_WIFI_DIRECT:
pDM_Odm->bWIFI_Direct = (bool)Value;
break;
@ -714,36 +708,20 @@ u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u
rate_bitmap = 0x00000ff5;
break;
case (ODM_WM_B | ODM_WM_G | ODM_WM_N24G):
if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
if (rssi_level == DM_RATR_STA_HIGH) {
rate_bitmap = 0x000f0000;
} else if (rssi_level == DM_RATR_STA_MIDDLE) {
rate_bitmap = 0x000ff000;
} else {
if (*pDM_Odm->pBandWidth == ODM_BW40M)
rate_bitmap = 0x000ff015;
else
rate_bitmap = 0x000ff005;
}
if (rssi_level == DM_RATR_STA_HIGH) {
rate_bitmap = 0x000f0000;
} else if (rssi_level == DM_RATR_STA_MIDDLE) {
rate_bitmap = 0x000ff000;
} else {
if (rssi_level == DM_RATR_STA_HIGH) {
rate_bitmap = 0x0f8f0000;
} else if (rssi_level == DM_RATR_STA_MIDDLE) {
rate_bitmap = 0x0f8ff000;
} else {
if (*pDM_Odm->pBandWidth == ODM_BW40M)
rate_bitmap = 0x0f8ff015;
else
rate_bitmap = 0x0f8ff005;
}
if (*pDM_Odm->pBandWidth == ODM_BW40M)
rate_bitmap = 0x000ff015;
else
rate_bitmap = 0x000ff005;
}
break;
default:
/* case WIRELESS_11_24N: */
if (pDM_Odm->RFType == RF_1T2R)
rate_bitmap = 0x000fffff;
else
rate_bitmap = 0x0fffffff;
rate_bitmap = 0x0fffffff;
break;
}

7
drivers/staging/r8188eu/hal/rtl8188e_dm.c
View File

@ -35,13 +35,6 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(hal_data->VersionID));
if (hal_data->rf_type == RF_1T1R)
ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
else if (hal_data->rf_type == RF_2T2R)
ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
else if (hal_data->rf_type == RF_1T2R)
ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType);
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |

14
drivers/staging/r8188eu/include/odm.h
View File

@ -229,7 +229,6 @@ enum odm_common_info_def {
/* HOOK BEFORE REG INIT----------- */
ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
ODM_CMNINFO_MP_TEST_CHIP,
ODM_CMNINFO_RF_TYPE, /* RF_PATH_E or ODM_RF_TYPE_E? */
/* HOOK BEFORE REG INIT----------- */
/* Dynamic value: */
@ -286,17 +285,6 @@ enum odm_ability_def {
# define ODM_ITRF_USB 0x2
enum odm_rf_type {
ODM_1T1R = 0,
ODM_1T2R = 1,
ODM_2T2R = 2,
ODM_2T3R = 3,
ODM_2T4R = 4,
ODM_3T3R = 5,
ODM_3T4R = 6,
ODM_4T4R = 7,
};
/* ODM_CMNINFO_OP_MODE */
enum odm_operation_mode {
ODM_NO_LINK = BIT(0),
@ -493,8 +481,6 @@ struct odm_dm_struct {
/* HOOK BEFORE REG INIT----------- */
/* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ <20>K<EFBFBD>K = 1/2/3/<2F>K */
u32 SupportAbility;
/* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
u8 RFType;
u32 BK_SupportAbility;
u8 AntDivType;