UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/msm/dsi: move min/max PLL rate to phy config 

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-9-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Dmitry Baryshkov 2021-03-31 13:57:19 +03:00 committed by Rob Clark
parent 80d2229bf0
commit 076437c9e3
8 changed files with 27 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
View File

@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg {
struct msm_dsi_phy_ops ops;
const struct msm_dsi_pll_ops pll_ops;
unsigned long min_pll_rate;
unsigned long max_pll_rate;
/*
* Each cell {phy_id, pll_id} of the truth table indicates
* if the source PLL selection bit should be set for each PHY.

6
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
View File

@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_10nm->postdiv_lock);
pll = &pll_10nm->base;
pll->min_rate = 1000000000UL;
pll->max_rate = 3500000000UL;
pll->cfg = phy->cfg;
pll_10nm->vco_delay = 1;
@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
};
@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,

6
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
View File

@ -1078,8 +1078,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_14nm->postdiv_lock);
pll = &pll_14nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
pll->cfg = phy->cfg;
pll_14nm->vco_delay = 1;
@ -1237,6 +1235,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2,
};
@ -1264,6 +1264,8 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.disable_seq = dsi_pll_14nm_disable_seq,
.enable_seq = dsi_pll_14nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0xc994400, 0xc996000 },
.num_dsi_phy = 2,
};

8
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
View File

@ -625,8 +625,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
}
pll = &pll_28nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
pll_28nm->vco_delay = 1000;
else
@ -811,6 +809,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2,
};
@ -837,6 +837,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_hpm,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2,
};
@ -863,6 +865,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq_lp,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
.quirks = DSI_PHY_28NM_QUIRK_PHY_LP,

4
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
View File

@ -508,8 +508,6 @@ static int dsi_pll_28nm_8960_init(struct msm_dsi_phy *phy)
}
pll = &pll_28nm->base;
pll->min_rate = VCO_MIN_RATE;
pll->max_rate = VCO_MAX_RATE;
pll->cfg = phy->cfg;
@ -711,6 +709,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.disable_seq = dsi_pll_28nm_disable_seq,
.enable_seq = dsi_pll_28nm_enable_seq,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2,
};

12
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
View File

@ -889,14 +889,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_7nm->postdiv_lock);
pll = &pll_7nm->base;
pll->min_rate = 1000000000UL;
pll->max_rate = 3500000000UL;
if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
pll->min_rate = 600000000UL;
pll->max_rate = (unsigned long)5000000000ULL;
/* workaround for max rate overflowing on 32-bit builds: */
pll->max_rate = max(pll->max_rate, 0xffffffffUL);
}
pll->cfg = phy->cfg;
pll_7nm->vco_delay = 1;
@ -1152,6 +1144,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.restore_state = dsi_pll_7nm_restore_state,
.set_usecase = dsi_pll_7nm_set_usecase,
},
.min_pll_rate = 600000000UL,
.max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_7NM_QUIRK_V4_1,
@ -1178,6 +1172,8 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.restore_state = dsi_pll_7nm_restore_state,
.set_usecase = dsi_pll_7nm_set_usecase,
},
.min_pll_rate = 1000000000UL,
.max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
};

8
drivers/gpu/drm/msm/dsi/phy/dsi_pll.c
View File

@ -14,10 +14,10 @@ long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
if (rate < pll->min_rate)
return pll->min_rate;
else if (rate > pll->max_rate)
return pll->max_rate;
if (rate < pll->cfg->min_pll_rate)
return pll->cfg->min_pll_rate;
else if (rate > pll->cfg->max_pll_rate)
return pll->cfg->max_pll_rate;
else
return rate;
}

3
drivers/gpu/drm/msm/dsi/phy/dsi_pll.h
View File

@ -18,9 +18,6 @@ struct msm_dsi_pll {
bool pll_on;
bool state_saved;
unsigned long min_rate;
unsigned long max_rate;
const struct msm_dsi_phy_cfg *cfg;
};