IOMMU Fixes for Linux v5.1-rc2
Including: - AMD IOMMU fix for sg-mapping with sg->offset > PAGE_SIZE - Fix for IOVA code to trigger the slow-path less often - Two fixes for Intel VT-d to avoid writing to read-onl registers and to flush the right domain id for the default domains in scalable mode -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAlyUxMcACgkQK/BELZcB GuPcUBAAsRaIicKz2HFsxfkGQawrTBlDCYi3xx8MndZ44ZHWk936CEli5nhSRDmd vCZPpl1j0HLfoUzoR4d/KEqYth+96Yh6h52e0WHh0ocIi5oJbIYZ7n8vwLT8lWQG X7QkT6Fx8+M3mNfuF1rY4Sa2ZexgeXQeitjip3ULXyvwqg3x7oj7KkRn6IM+hRIv BlCZXJNnjVQplWP4w/6j1BE5OtP1yDYCi3exOYO2A+2CIa7VHybOj+Ry2nEPYAAk GvZ7kNgQwxov1626QrIp8antqswtTODUqm7x7mdCfoEqX7LPEqKKs578wkHqvIis R8GpJxW0RI6OSSXBrRjhOhM2sgQL4csiLiMijZORGnN1jSyurY6Cdjxu24+3Gd0e 25GIYJgR5U39Uf+g/1CIBAooPoV/sUhOVmAk0HTQvnvx7kXAzdCcIpRcU1H2k0nZ XaO/+KCuTnWbhbsdKCUmigtgs+zf1x7fkamiGp9d+rO4PlZn8UnMg6JnS0IuZVE8 gvWY5orXQx5izb3JJGLD3u21/UKq+nM8+VqN1++piCy9Vu2BPJBvabgAq7iC0Xax CfF+5migNNfC1PMgA49LAPAyRf/CwWO1H364IyK2avAeFHCXiPSqWZ/2Urbxp2zc u946DsMGDxo6Wamp+s2TzXbpHZ5CbSsjLNE8PhuxDjJXwVpaDOU= =wkBN -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: - AMD IOMMU fix for sg-mapping with sg->offset > PAGE_SIZE - Fix for IOVA code to trigger the slow-path less often - Two fixes for Intel VT-d to avoid writing to read-only registers and to flush the right domain id for the default domains in scalable mode * tag 'iommu-fixes-v5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/vt-d: Save the right domain ID used by hardware iommu/vt-d: Check capability before disabling protected memory iommu/iova: Fix tracking of recently failed iova address iommu/amd: fix sg->dma_address for sg->offset bigger than PAGE_SIZE
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commit
070c95d457
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@ -2608,7 +2608,12 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
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/* Everything is mapped - write the right values into s->dma_address */
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for_each_sg(sglist, s, nelems, i) {
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s->dma_address += address + s->offset;
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/*
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* Add in the remaining piece of the scatter-gather offset that
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* was masked out when we were determining the physical address
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* via (sg_phys(s) & PAGE_MASK) earlier.
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*/
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s->dma_address += address + (s->offset & ~PAGE_MASK);
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s->dma_length = s->length;
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}
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@ -1538,6 +1538,9 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
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u32 pmen;
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unsigned long flags;
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if (!cap_plmr(iommu->cap) && !cap_phmr(iommu->cap))
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return;
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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pmen = readl(iommu->reg + DMAR_PMEN_REG);
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pmen &= ~DMA_PMEN_EPM;
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@ -5332,7 +5335,7 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd
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ctx_lo = context[0].lo;
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sdev->did = domain->iommu_did[iommu->seq_id];
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sdev->did = FLPT_DEFAULT_DID;
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sdev->sid = PCI_DEVID(info->bus, info->devfn);
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if (!(ctx_lo & CONTEXT_PASIDE)) {
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@ -207,8 +207,10 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,
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curr_iova = rb_entry(curr, struct iova, node);
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} while (curr && new_pfn <= curr_iova->pfn_hi);
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if (limit_pfn < size || new_pfn < iovad->start_pfn)
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if (limit_pfn < size || new_pfn < iovad->start_pfn) {
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iovad->max32_alloc_size = size;
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goto iova32_full;
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}
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/* pfn_lo will point to size aligned address if size_aligned is set */
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new->pfn_lo = new_pfn;
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@ -222,7 +224,6 @@ static int __alloc_and_insert_iova_range(struct iova_domain *iovad,
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return 0;
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iova32_full:
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iovad->max32_alloc_size = size;
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spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
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return -ENOMEM;
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}
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