IOMMU Fixes for Linux v6.0-rc6
Including: - Two fixes for Intel VT-d: - Check the right capability bit for 5-level page table support. - Revert a previous fix which caused a regression with Thunderbolt devices. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmMrAH4ACgkQK/BELZcB GuODfQ//RlhWICLj1a1RhBoZ5aUpWsuCrPd0GAdi7scgK7qVeBqcN/ZWfrlrtekD Ogxos+cFi/L5V2JhYRKP9/qfh6U/29ZAK85NNErcYko6WHmSsjOI++pyMrzng9cX RMbePTgoElTRn/3kGC8AS0tTvLAMKo4sznYPZw9AygCaBc/YkwGeK0qDxTPKhzfd GpVZxarKZvr5flQ0YgQE9DLtVdIfzSl5FXR2gIT1E8+6KRCX8XeTsj9C821qRxpo rmf6Xmbzc+oLsJ57/qiOgorrBiu5PRWz+eDIhbPUQ7B9tl+HT96VP+45i3qTC0ig au4M9NQQRo/hCq3gx236oO0Nqt9c5FLbpDG2+SoroYsCjNSdOpNUhtqylVSJOi8i sCeiLZop0RckLyrst0kny7SxJNRtNEw4XDGhZCfHBnv/vxCFUOWgqI6rOlOH4j/f KCs2jYPOghp+GZv7yVHLq/cjkhNgPW9EQeqpYrX/y29kxgmOQM4rpZlra70qQAlH NbJBCtlOLTOniGAJgAAMORFIMWtttfhV0cucu8vQKXKnhzGn+4hpZkaNHyI3vl3S upJ7i0t6TyghyeuUhWpF21KHc83d0Nd/fWVFstngJ4XhfNJFhqddOHaYsABK7Czk QezpvKaNFNxAPe08CbMp8bjVEQdPhJ7oRvcLjSUSVtLxOrVebcw= =sUtt -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v6.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: "Two fixes for Intel VT-d: - Check the right capability bit for 5-level page table support. - Revert a previous fix which caused a regression with Thunderbolt devices" * tag 'iommu-fixes-v6.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/vt-d: Check correct capability for sagaw determination Revert "iommu/vt-d: Fix possible recursive locking in intel_iommu_init()"
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06f7db9499
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@ -2349,13 +2349,6 @@ static int dmar_device_hotplug(acpi_handle handle, bool insert)
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if (!dmar_in_use())
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return 0;
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/*
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* It's unlikely that any I/O board is hot added before the IOMMU
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* subsystem is initialized.
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*/
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if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled)
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return -EOPNOTSUPP;
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if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
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tmp = handle;
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} else {
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@ -399,7 +399,7 @@ static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu)
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{
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unsigned long fl_sagaw, sl_sagaw;
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fl_sagaw = BIT(2) | (cap_fl1gp_support(iommu->cap) ? BIT(3) : 0);
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fl_sagaw = BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0);
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sl_sagaw = cap_sagaw(iommu->cap);
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/* Second level only. */
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@ -3019,7 +3019,13 @@ static int __init init_dmars(void)
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#ifdef CONFIG_INTEL_IOMMU_SVM
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if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) {
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/*
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* Call dmar_alloc_hwirq() with dmar_global_lock held,
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* could cause possible lock race condition.
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*/
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up_write(&dmar_global_lock);
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ret = intel_svm_enable_prq(iommu);
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down_write(&dmar_global_lock);
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if (ret)
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goto free_iommu;
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}
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@ -3932,6 +3938,7 @@ int __init intel_iommu_init(void)
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force_on = (!intel_iommu_tboot_noforce && tboot_force_iommu()) ||
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platform_optin_force_iommu();
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down_write(&dmar_global_lock);
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if (dmar_table_init()) {
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if (force_on)
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panic("tboot: Failed to initialize DMAR table\n");
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@ -3944,6 +3951,16 @@ int __init intel_iommu_init(void)
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goto out_free_dmar;
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}
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up_write(&dmar_global_lock);
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/*
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* The bus notifier takes the dmar_global_lock, so lockdep will
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* complain later when we register it under the lock.
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*/
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dmar_register_bus_notifier();
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down_write(&dmar_global_lock);
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if (!no_iommu)
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intel_iommu_debugfs_init();
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@ -3988,9 +4005,11 @@ int __init intel_iommu_init(void)
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pr_err("Initialization failed\n");
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goto out_free_dmar;
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}
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up_write(&dmar_global_lock);
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init_iommu_pm_ops();
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down_read(&dmar_global_lock);
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for_each_active_iommu(iommu, drhd) {
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/*
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* The flush queue implementation does not perform
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@ -4008,11 +4027,13 @@ int __init intel_iommu_init(void)
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"%s", iommu->name);
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iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
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}
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up_read(&dmar_global_lock);
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bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
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if (si_domain && !hw_pass_through)
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register_memory_notifier(&intel_iommu_memory_nb);
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down_read(&dmar_global_lock);
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if (probe_acpi_namespace_devices())
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pr_warn("ACPI name space devices didn't probe correctly\n");
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@ -4023,15 +4044,17 @@ int __init intel_iommu_init(void)
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iommu_disable_protect_mem_regions(iommu);
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}
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up_read(&dmar_global_lock);
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pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
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intel_iommu_enabled = 1;
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dmar_register_bus_notifier();
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pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
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return 0;
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out_free_dmar:
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intel_iommu_free_dmars();
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up_write(&dmar_global_lock);
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return ret;
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}
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@ -65,7 +65,6 @@ struct dmar_pci_notify_info {
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extern struct rw_semaphore dmar_global_lock;
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extern struct list_head dmar_drhd_units;
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extern int intel_iommu_enabled;
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
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@ -89,8 +88,7 @@ extern int intel_iommu_enabled;
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static inline bool dmar_rcu_check(void)
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{
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return rwsem_is_locked(&dmar_global_lock) ||
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system_state == SYSTEM_BOOTING ||
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(IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled);
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system_state == SYSTEM_BOOTING;
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}
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#define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
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