arm64: dts: imx8: correct clock order
Per bindings/mmc/fsl-imx-esdhc.yaml, the clock order is ipg, ahb, per,
otherwise warning: "
mmc@5b020000: clock-names:1: 'ahb' was expected
mmc@5b020000: clock-names:2: 'per' was expected "
Fixes: 16c4ea7501
("arm64: dts: imx8: switch to new lpcg clock binding")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
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@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 {
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
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<&sdhc0_lpcg IMX_LPCG_CLK_5>,
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<&sdhc0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per", "ahb";
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<&sdhc0_lpcg IMX_LPCG_CLK_0>,
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<&sdhc0_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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status = "disabled";
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};
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@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 {
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b020000 0x10000>;
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clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
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<&sdhc1_lpcg IMX_LPCG_CLK_5>,
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<&sdhc1_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per", "ahb";
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<&sdhc1_lpcg IMX_LPCG_CLK_0>,
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<&sdhc1_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_1>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step = <2>;
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@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 {
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b030000 0x10000>;
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clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
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<&sdhc2_lpcg IMX_LPCG_CLK_5>,
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<&sdhc2_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "per", "ahb";
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<&sdhc2_lpcg IMX_LPCG_CLK_0>,
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<&sdhc2_lpcg IMX_LPCG_CLK_5>;
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clock-names = "ipg", "ahb", "per";
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power-domains = <&pd IMX_SC_R_SDHC_2>;
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status = "disabled";
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};
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