[media] s5p-tv: fix mbus configuration
This patch fixes mbus configuration between Mixer, SDO and HDMI. The SDO accepts only YUV444 on input. The HDMI in DVI mode accepts only RGB888. Now Mixer is choosing proper output format depending on mbus format. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -440,6 +440,7 @@ static const struct hdmi_preset_conf hdmi_conf_480p = {
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.height = 480,
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.height = 480,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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},
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};
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};
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@ -472,6 +473,7 @@ static const struct hdmi_preset_conf hdmi_conf_720p60 = {
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.height = 720,
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.height = 720,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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},
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};
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};
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@ -504,6 +506,7 @@ static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
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.height = 1080,
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.height = 1080,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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},
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};
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};
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@ -536,6 +539,7 @@ static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
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.height = 1080,
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.height = 1080,
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
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.field = V4L2_FIELD_NONE,
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.field = V4L2_FIELD_NONE,
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.colorspace = V4L2_COLORSPACE_SRGB,
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},
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},
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};
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};
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@ -90,7 +90,7 @@ void mxr_reg_reset(struct mxr_device *mdev)
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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/* set output in RGB888 mode */
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/* set output in RGB888 mode */
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mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_YUV444);
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mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
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/* 16 beat burst in DMA */
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/* 16 beat burst in DMA */
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mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
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mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
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@ -376,6 +376,12 @@ void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
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spin_lock_irqsave(&mdev->reg_slock, flags);
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spin_lock_irqsave(&mdev->reg_slock, flags);
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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/* selecting colorspace accepted by output */
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if (fmt->colorspace == V4L2_COLORSPACE_JPEG)
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val |= MXR_CFG_OUT_YUV444;
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else
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val |= MXR_CFG_OUT_RGB888;
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/* choosing between interlace and progressive mode */
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/* choosing between interlace and progressive mode */
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if (fmt->field == V4L2_FIELD_INTERLACED)
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if (fmt->field == V4L2_FIELD_INTERLACED)
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val |= MXR_CFG_SCAN_INTERLACE;
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val |= MXR_CFG_SCAN_INTERLACE;
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@ -394,7 +400,8 @@ void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
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else
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else
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WARN(1, "unrecognized mbus height %u!\n", fmt->height);
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WARN(1, "unrecognized mbus height %u!\n", fmt->height);
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mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK);
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mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
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MXR_CFG_OUT_MASK);
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val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
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val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
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vp_write_mask(mdev, VP_MODE, val,
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vp_write_mask(mdev, VP_MODE, val,
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@ -67,6 +67,7 @@
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/* bits for MXR_CFG */
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/* bits for MXR_CFG */
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#define MXR_CFG_OUT_YUV444 (0 << 8)
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#define MXR_CFG_OUT_YUV444 (0 << 8)
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#define MXR_CFG_OUT_RGB888 (1 << 8)
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#define MXR_CFG_OUT_RGB888 (1 << 8)
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#define MXR_CFG_OUT_MASK (1 << 8)
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#define MXR_CFG_DST_SDO (0 << 7)
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#define MXR_CFG_DST_SDO (0 << 7)
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#define MXR_CFG_DST_HDMI (1 << 7)
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#define MXR_CFG_DST_HDMI (1 << 7)
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#define MXR_CFG_DST_MASK (1 << 7)
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#define MXR_CFG_DST_MASK (1 << 7)
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@ -170,6 +170,7 @@ static int sdo_g_mbus_fmt(struct v4l2_subdev *sd,
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fmt->height = sdev->fmt->height;
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fmt->height = sdev->fmt->height;
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fmt->code = V4L2_MBUS_FMT_FIXED;
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fmt->code = V4L2_MBUS_FMT_FIXED;
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fmt->field = V4L2_FIELD_INTERLACED;
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fmt->field = V4L2_FIELD_INTERLACED;
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fmt->colorspace = V4L2_COLORSPACE_JPEG;
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return 0;
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return 0;
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}
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}
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