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drm/amdgpu/sdma5: add placeholder for navi14 golden settings 

To be filled in once they are available.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojie Yuan 2018-12-17 18:07:22 +08:00 committed by Alex Deucher
parent 6041f2a281
commit 06823925ad
1 changed files with 11 additions and 0 deletions
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11
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
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@ -85,6 +85,9 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
}; };
static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
};
static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
{ {
u32 base; u32 base;
@ -114,6 +117,14 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_nv10, golden_settings_sdma_nv10,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
break; break;
case CHIP_NAVI14:
soc15_program_register_sequence(adev,
golden_settings_sdma_5,
(const u32)ARRAY_SIZE(golden_settings_sdma_5));
soc15_program_register_sequence(adev,
golden_settings_sdma_nv14,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
break;
default: default:
break; break;
} }