Merge branch 'fixes' into next
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commit
0662d797d5
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@ -17,6 +17,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/interconnect.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/reset.h>
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#include "sdhci-pltfm.h"
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#include "cqhci.h"
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@ -2507,6 +2508,43 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
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of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
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}
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static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
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{
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struct reset_control *reset;
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int ret = 0;
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reset = reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(reset))
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return dev_err_probe(dev, PTR_ERR(reset),
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"unable to acquire core_reset\n");
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if (!reset)
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return ret;
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ret = reset_control_assert(reset);
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if (ret) {
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reset_control_put(reset);
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return dev_err_probe(dev, ret, "core_reset assert failed\n");
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}
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/*
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* The hardware requirement for delay between assert/deassert
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* is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
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* ~125us (4/32768). To be on the safe side add 200us delay.
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*/
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usleep_range(200, 210);
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ret = reset_control_deassert(reset);
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if (ret) {
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reset_control_put(reset);
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return dev_err_probe(dev, ret, "core_reset deassert failed\n");
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}
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usleep_range(200, 210);
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reset_control_put(reset);
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return ret;
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}
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static int sdhci_msm_probe(struct platform_device *pdev)
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{
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@ -2554,6 +2592,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
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ret = sdhci_msm_gcc_reset(&pdev->dev, host);
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if (ret)
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goto pltfm_free;
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/* Setup SDCC bus voter clock. */
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msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (!IS_ERR(msm_host->bus_clk)) {
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