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drm/i915/guc: Kill USES_GUC_SUBMISSION macro 

use intel_uc_uses_guc_submission() directly instead, to be consistent in
the way we check what we want to do with the GuC.

v2: do not go through ctx->vm->gt, use i915->gt instead

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> #v1
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200218223327.11058-3-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio 2020-02-18 14:33:20 -08:00 committed by Chris Wilson
parent 34bbfde606
commit 065273f76d
8 changed files with 15 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/gem/i915_gem_context.c
View File

@ -1390,7 +1390,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data)
if (!HAS_EXECLISTS(i915))
return -ENODEV;
if (USES_GUC_SUBMISSION(i915))
if (intel_uc_uses_guc_submission(&i915->gt.uc))
return -ENODEV; /* not implement yet */
if (get_user(idx, &ext->engine_index))

2
drivers/gpu/drm/i915/gt/selftest_hangcheck.c
View File

@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
igt_global_reset_lock(gt);

12
drivers/gpu/drm/i915/gt/selftest_lrc.c
View File

@ -2109,7 +2109,7 @@ static int live_suppress_self_preempt(void *arg)
if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
return 0;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0; /* presume black blox */
if (intel_vgpu_active(gt->i915))
@ -3224,7 +3224,7 @@ static int live_virtual_engine(void *arg)
unsigned int class, inst;
int err;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
for_each_engine(engine, gt, id) {
@ -3357,7 +3357,7 @@ static int live_virtual_mask(void *arg)
unsigned int class, inst;
int err;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
@ -3499,7 +3499,7 @@ static int live_virtual_preserved(void *arg)
* are preserved.
*/
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
/* As we use CS_GPR we cannot run before they existed on all engines. */
@ -3729,7 +3729,7 @@ static int live_virtual_bond(void *arg)
unsigned int class, inst;
int err;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
@ -3890,7 +3890,7 @@ static int live_virtual_reset(void *arg)
* forgotten.
*/
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
if (!intel_has_reset_engine(gt))

2
drivers/gpu/drm/i915/gt/selftest_reset.c
View File

@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
if (USES_GUC_SUBMISSION(gt->i915))
if (intel_uc_uses_guc_submission(&gt->uc))
return 0;
intel_gt_pm_get(gt);

3
drivers/gpu/drm/i915/gvt/scheduler.c
View File

@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
ce->vm = i915_vm_get(&ppgtt->vm);
intel_context_set_single_submission(ce);
if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
/* Max ring buffer size */
if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
const unsigned int ring_size = 512 * SZ_4K;
ce->ring = __intel_context_ring_size(ring_size);

6
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -1573,11 +1573,11 @@ static int i915_guc_info(struct seq_file *m, void *data)
static int i915_guc_stage_pool(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = &dev_priv->gt.uc.guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
struct intel_uc *uc = &dev_priv->gt.uc;
struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
int index;
if (!USES_GUC_SUBMISSION(dev_priv))
if (!intel_uc_uses_guc_submission(uc))
return -ENODEV;
for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1692,9 +1692,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)

2
drivers/gpu/drm/i915/intel_gvt.c
View File

@ -105,7 +105,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
if (USES_GUC_SUBMISSION(dev_priv)) {
if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
drm_err(&dev_priv->drm,
"i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
return -EIO;