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clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS 

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
	unsigned int num;
	struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Neil Armstrong 2023-06-12 11:57:23 +02:00 committed by Jerome Brunet
parent 5e4e480466
commit 05d3b7c68e
3 changed files with 424 additions and 428 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/meson/Kconfig
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@ -100,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO
select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PHASE select COMMON_CLK_MESON_PHASE
select COMMON_CLK_MESON_SCLK_DIV select COMMON_CLK_MESON_SCLK_DIV
select COMMON_CLK_MESON_CLKC_UTILS
select REGMAP_MMIO select REGMAP_MMIO
help help
Support for the audio clock controller on AmLogic A113D devices, Support for the audio clock controller on AmLogic A113D devices,

43
drivers/clk/meson/axg-audio.c
View File

@ -15,6 +15,7 @@
#include <linux/reset-controller.h> #include <linux/reset-controller.h>
#include <linux/slab.h> #include <linux/slab.h>
#include "meson-clkc-utils.h"
#include "axg-audio.h" #include "axg-audio.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "clk-phase.h" #include "clk-phase.h"
@ -811,8 +812,7 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
* Array of all clocks provided by this provider * Array of all clocks provided by this provider
* The input clocks of the controller will be populated at runtime * The input clocks of the controller will be populated at runtime
*/ */
static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { static struct clk_hw *axg_audio_hw_clks[] = {
.hws = {
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw, [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
[AUD_CLKID_PDM] = &pdm.hw, [AUD_CLKID_PDM] = &pdm.hw,
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw, [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
@ -935,17 +935,13 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
[AUD_CLKID_TOP] = &axg_aud_top, [AUD_CLKID_TOP] = &axg_aud_top,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
}; };
/* /*
* Array of all G12A clocks provided by this provider * Array of all G12A clocks provided by this provider
* The input clocks of the controller will be populated at runtime * The input clocks of the controller will be populated at runtime
*/ */
static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = { static struct clk_hw *g12a_audio_hw_clks[] = {
.hws = {
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw, [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
[AUD_CLKID_PDM] = &pdm.hw, [AUD_CLKID_PDM] = &pdm.hw,
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw, [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
@ -1080,17 +1076,13 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
[AUD_CLKID_TOP] = &axg_aud_top, [AUD_CLKID_TOP] = &axg_aud_top,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
}; };
/* /*
* Array of all SM1 clocks provided by this provider * Array of all SM1 clocks provided by this provider
* The input clocks of the controller will be populated at runtime * The input clocks of the controller will be populated at runtime
*/ */
static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = { static struct clk_hw *sm1_audio_hw_clks[] = {
.hws = {
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw, [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
[AUD_CLKID_PDM] = &pdm.hw, [AUD_CLKID_PDM] = &pdm.hw,
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw, [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
@ -1238,9 +1230,6 @@ static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
[AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw, [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
[AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw, [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
[AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw, [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
}; };
@ -1745,7 +1734,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
struct audioclk_data { struct audioclk_data {
struct clk_regmap *const *regmap_clks; struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num; unsigned int regmap_clk_num;
struct clk_hw_onecell_data *hw_onecell_data; struct meson_clk_hw_data hw_clks;
unsigned int reset_offset; unsigned int reset_offset;
unsigned int reset_num; unsigned int reset_num;
}; };
@ -1791,10 +1780,10 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
data->regmap_clks[i]->map = map; data->regmap_clks[i]->map = map;
/* Take care to skip the registered input clocks */ /* Take care to skip the registered input clocks */
for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) { for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
const char *name; const char *name;
hw = data->hw_onecell_data->hws[i]; hw = data->hw_clks.hws[i];
/* array might be sparse */ /* array might be sparse */
if (!hw) if (!hw)
continue; continue;
@ -1808,8 +1797,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
} }
} }
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
data->hw_onecell_data);
if (ret) if (ret)
return ret; return ret;
@ -1834,13 +1822,19 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
static const struct audioclk_data axg_audioclk_data = { static const struct audioclk_data axg_audioclk_data = {
.regmap_clks = axg_clk_regmaps, .regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
.hw_onecell_data = &axg_audio_hw_onecell_data, .hw_clks = {
.hws = axg_audio_hw_clks,
.num = ARRAY_SIZE(axg_audio_hw_clks),
},
}; };
static const struct audioclk_data g12a_audioclk_data = { static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = g12a_clk_regmaps, .regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_onecell_data = &g12a_audio_hw_onecell_data, .hw_clks = {
.hws = g12a_audio_hw_clks,
.num = ARRAY_SIZE(g12a_audio_hw_clks),
},
.reset_offset = AUDIO_SW_RESET, .reset_offset = AUDIO_SW_RESET,
.reset_num = 26, .reset_num = 26,
}; };
@ -1848,7 +1842,10 @@ static const struct audioclk_data g12a_audioclk_data = {
static const struct audioclk_data sm1_audioclk_data = { static const struct audioclk_data sm1_audioclk_data = {
.regmap_clks = sm1_clk_regmaps, .regmap_clks = sm1_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
.hw_onecell_data = &sm1_audio_hw_onecell_data, .hw_clks = {
.hws = sm1_audio_hw_clks,
.num = ARRAY_SIZE(sm1_audio_hw_clks),
},
.reset_offset = AUDIO_SM1_SW_RESET0, .reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39, .reset_num = 39,
}; };

2
drivers/clk/meson/axg-audio.h
View File

@ -138,6 +138,4 @@
/* include the CLKIDs which are part of the DT bindings */ /* include the CLKIDs which are part of the DT bindings */
#include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/axg-audio-clkc.h>
#define NR_CLKS 178
#endif /*__AXG_AUDIO_CLKC_H */ #endif /*__AXG_AUDIO_CLKC_H */