MIPS: kernel: unaligned: Add support for the MIPS R6
The load/store unaligned instructions have been removed in MIPS R6 so we need to re-implement the related macros using the regular load/store instructions. Moreover, the load/store from coprocessor 2 instructions have been reallocated in Release 6 so we will handle them in the emulator instead. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin
Markos Chandras
parent
acac4108df
commit
0593a44c64
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@ -129,6 +129,7 @@ extern void show_registers(struct pt_regs *regs);
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#ifndef CONFIG_CPU_MIPSR6
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#define LoadW(addr, value, res) \
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__asm__ __volatile__ ( \
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"1:\t"user_lwl("%0", "(%2)")"\n" \
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@ -146,6 +147,39 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#else
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/* MIPSR6 has no lwl instruction */
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#define LoadW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n" \
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".set\tnoat\n\t" \
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"1:"user_lb("%0", "0(%2)")"\n\t" \
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"2:"user_lbu("$1", "1(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:"user_lbu("$1", "2(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:"user_lbu("$1", "3(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"li\t%1, 0\n" \
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".set\tpop\n" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%1, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#endif /* CONFIG_CPU_MIPSR6 */
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#define LoadHWU(addr, value, res) \
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__asm__ __volatile__ ( \
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@ -169,6 +203,7 @@ extern void show_registers(struct pt_regs *regs);
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#ifndef CONFIG_CPU_MIPSR6
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#define LoadWU(addr, value, res) \
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__asm__ __volatile__ ( \
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"1:\t"user_lwl("%0", "(%2)")"\n" \
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@ -206,6 +241,87 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#define LoadWU(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:"user_lbu("%0", "0(%2)")"\n\t" \
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"2:"user_lbu("$1", "1(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:"user_lbu("$1", "2(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:"user_lbu("$1", "3(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"li\t%1, 0\n" \
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".set\tpop\n" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%1, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#define LoadDW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:lb\t%0, 0(%2)\n\t" \
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"2:lbu\t $1, 1(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:lbu\t$1, 2(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:lbu\t$1, 3(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"5:lbu\t$1, 4(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"6:lbu\t$1, 5(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"7:lbu\t$1, 6(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"8:lbu\t$1, 7(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"li\t%1, 0\n" \
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".set\tpop\n\t" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%1, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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STR(PTR)"\t5b, 11b\n\t" \
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STR(PTR)"\t6b, 11b\n\t" \
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STR(PTR)"\t7b, 11b\n\t" \
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STR(PTR)"\t8b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#endif /* CONFIG_CPU_MIPSR6 */
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#define StoreHW(addr, value, res) \
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__asm__ __volatile__ ( \
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@ -228,6 +344,7 @@ extern void show_registers(struct pt_regs *regs);
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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#ifndef CONFIG_CPU_MIPSR6
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#define StoreW(addr, value, res) \
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__asm__ __volatile__ ( \
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"1:\t"user_swl("%1", "(%2)")"\n" \
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@ -263,9 +380,82 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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#endif
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#else
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/* MIPSR6 has no swl and sdl instructions */
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#define StoreW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:"user_sb("%1", "3(%2)")"\n\t" \
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"srl\t$1, %1, 0x8\n\t" \
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"2:"user_sb("$1", "2(%2)")"\n\t" \
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"srl\t$1, $1, 0x8\n\t" \
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"3:"user_sb("$1", "1(%2)")"\n\t" \
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"srl\t$1, $1, 0x8\n\t" \
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"4:"user_sb("$1", "0(%2)")"\n\t" \
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".set\tpop\n\t" \
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"li\t%0, 0\n" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%0, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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#define StoreDW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:sb\t%1, 7(%2)\n\t" \
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"dsrl\t$1, %1, 0x8\n\t" \
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"2:sb\t$1, 6(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"3:sb\t$1, 5(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"4:sb\t$1, 4(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"5:sb\t$1, 3(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"6:sb\t$1, 2(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"7:sb\t$1, 1(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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"8:sb\t$1, 0(%2)\n\t" \
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"dsrl\t$1, $1, 0x8\n\t" \
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".set\tpop\n\t" \
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"li\t%0, 0\n" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%0, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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STR(PTR)"\t5b, 11b\n\t" \
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STR(PTR)"\t6b, 11b\n\t" \
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STR(PTR)"\t7b, 11b\n\t" \
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STR(PTR)"\t8b, 11b\n\t" \
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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#endif /* CONFIG_CPU_MIPSR6 */
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#else /* __BIG_ENDIAN */
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#ifdef __LITTLE_ENDIAN
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#define LoadHW(addr, value, res) \
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__asm__ __volatile__ (".set\tnoat\n" \
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"1:\t"user_lb("%0", "1(%2)")"\n" \
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@ -286,6 +476,7 @@ extern void show_registers(struct pt_regs *regs);
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#ifndef CONFIG_CPU_MIPSR6
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#define LoadW(addr, value, res) \
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__asm__ __volatile__ ( \
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"1:\t"user_lwl("%0", "3(%2)")"\n" \
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@ -303,6 +494,40 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#else
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/* MIPSR6 has no lwl instruction */
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#define LoadW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n" \
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".set\tnoat\n\t" \
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"1:"user_lb("%0", "3(%2)")"\n\t" \
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"2:"user_lbu("$1", "2(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:"user_lbu("$1", "1(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:"user_lbu("$1", "0(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"li\t%1, 0\n" \
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".set\tpop\n" \
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"10:\n\t" \
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".insn\n\t" \
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".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%1, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#endif /* CONFIG_CPU_MIPSR6 */
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#define LoadHWU(addr, value, res) \
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__asm__ __volatile__ ( \
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@ -326,6 +551,7 @@ extern void show_registers(struct pt_regs *regs);
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#ifndef CONFIG_CPU_MIPSR6
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#define LoadWU(addr, value, res) \
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__asm__ __volatile__ ( \
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"1:\t"user_lwl("%0", "3(%2)")"\n" \
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@ -363,6 +589,86 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#define LoadWU(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:"user_lbu("%0", "3(%2)")"\n\t" \
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"2:"user_lbu("$1", "2(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:"user_lbu("$1", "1(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:"user_lbu("$1", "0(%2)")"\n\t" \
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"sll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"li\t%1, 0\n" \
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".set\tpop\n" \
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"10:\n\t" \
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".insn\n\t" \
|
||||
".section\t.fixup,\"ax\"\n\t" \
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"11:\tli\t%1, %3\n\t" \
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"j\t10b\n\t" \
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".previous\n\t" \
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".section\t__ex_table,\"a\"\n\t" \
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STR(PTR)"\t1b, 11b\n\t" \
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STR(PTR)"\t2b, 11b\n\t" \
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STR(PTR)"\t3b, 11b\n\t" \
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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#define LoadDW(addr, value, res) \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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"1:lb\t%0, 7(%2)\n\t" \
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"2:lbu\t$1, 6(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"3:lbu\t$1, 5(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"4:lbu\t$1, 4(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
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"5:lbu\t$1, 3(%2)\n\t" \
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"dsll\t%0, 0x8\n\t" \
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"or\t%0, $1\n\t" \
|
||||
"6:lbu\t$1, 2(%2)\n\t" \
|
||||
"dsll\t%0, 0x8\n\t" \
|
||||
"or\t%0, $1\n\t" \
|
||||
"7:lbu\t$1, 1(%2)\n\t" \
|
||||
"dsll\t%0, 0x8\n\t" \
|
||||
"or\t%0, $1\n\t" \
|
||||
"8:lbu\t$1, 0(%2)\n\t" \
|
||||
"dsll\t%0, 0x8\n\t" \
|
||||
"or\t%0, $1\n\t" \
|
||||
"li\t%1, 0\n" \
|
||||
".set\tpop\n\t" \
|
||||
"10:\n\t" \
|
||||
".insn\n\t" \
|
||||
".section\t.fixup,\"ax\"\n\t" \
|
||||
"11:\tli\t%1, %3\n\t" \
|
||||
"j\t10b\n\t" \
|
||||
".previous\n\t" \
|
||||
".section\t__ex_table,\"a\"\n\t" \
|
||||
STR(PTR)"\t1b, 11b\n\t" \
|
||||
STR(PTR)"\t2b, 11b\n\t" \
|
||||
STR(PTR)"\t3b, 11b\n\t" \
|
||||
STR(PTR)"\t4b, 11b\n\t" \
|
||||
STR(PTR)"\t5b, 11b\n\t" \
|
||||
STR(PTR)"\t6b, 11b\n\t" \
|
||||
STR(PTR)"\t7b, 11b\n\t" \
|
||||
STR(PTR)"\t8b, 11b\n\t" \
|
||||
".previous" \
|
||||
: "=&r" (value), "=r" (res) \
|
||||
: "r" (addr), "i" (-EFAULT));
|
||||
#endif /* CONFIG_CPU_MIPSR6 */
|
||||
|
||||
#define StoreHW(addr, value, res) \
|
||||
__asm__ __volatile__ ( \
|
||||
|
|
@ -384,7 +690,7 @@ extern void show_registers(struct pt_regs *regs);
|
|||
".previous" \
|
||||
: "=r" (res) \
|
||||
: "r" (value), "r" (addr), "i" (-EFAULT));
|
||||
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
#define StoreW(addr, value, res) \
|
||||
__asm__ __volatile__ ( \
|
||||
"1:\t"user_swl("%1", "3(%2)")"\n" \
|
||||
|
|
@ -420,6 +726,79 @@ extern void show_registers(struct pt_regs *regs);
|
|||
".previous" \
|
||||
: "=r" (res) \
|
||||
: "r" (value), "r" (addr), "i" (-EFAULT));
|
||||
#else
|
||||
/* MIPSR6 has no swl and sdl instructions */
|
||||
#define StoreW(addr, value, res) \
|
||||
__asm__ __volatile__ ( \
|
||||
".set\tpush\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"1:"user_sb("%1", "0(%2)")"\n\t" \
|
||||
"srl\t$1, %1, 0x8\n\t" \
|
||||
"2:"user_sb("$1", "1(%2)")"\n\t" \
|
||||
"srl\t$1, $1, 0x8\n\t" \
|
||||
"3:"user_sb("$1", "2(%2)")"\n\t" \
|
||||
"srl\t$1, $1, 0x8\n\t" \
|
||||
"4:"user_sb("$1", "3(%2)")"\n\t" \
|
||||
".set\tpop\n\t" \
|
||||
"li\t%0, 0\n" \
|
||||
"10:\n\t" \
|
||||
".insn\n\t" \
|
||||
".section\t.fixup,\"ax\"\n\t" \
|
||||
"11:\tli\t%0, %3\n\t" \
|
||||
"j\t10b\n\t" \
|
||||
".previous\n\t" \
|
||||
".section\t__ex_table,\"a\"\n\t" \
|
||||
STR(PTR)"\t1b, 11b\n\t" \
|
||||
STR(PTR)"\t2b, 11b\n\t" \
|
||||
STR(PTR)"\t3b, 11b\n\t" \
|
||||
STR(PTR)"\t4b, 11b\n\t" \
|
||||
".previous" \
|
||||
: "=&r" (res) \
|
||||
: "r" (value), "r" (addr), "i" (-EFAULT) \
|
||||
: "memory");
|
||||
|
||||
#define StoreDW(addr, value, res) \
|
||||
__asm__ __volatile__ ( \
|
||||
".set\tpush\n\t" \
|
||||
".set\tnoat\n\t" \
|
||||
"1:sb\t%1, 0(%2)\n\t" \
|
||||
"dsrl\t$1, %1, 0x8\n\t" \
|
||||
"2:sb\t$1, 1(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"3:sb\t$1, 2(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"4:sb\t$1, 3(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"5:sb\t$1, 4(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"6:sb\t$1, 5(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"7:sb\t$1, 6(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
"8:sb\t$1, 7(%2)\n\t" \
|
||||
"dsrl\t$1, $1, 0x8\n\t" \
|
||||
".set\tpop\n\t" \
|
||||
"li\t%0, 0\n" \
|
||||
"10:\n\t" \
|
||||
".insn\n\t" \
|
||||
".section\t.fixup,\"ax\"\n\t" \
|
||||
"11:\tli\t%0, %3\n\t" \
|
||||
"j\t10b\n\t" \
|
||||
".previous\n\t" \
|
||||
".section\t__ex_table,\"a\"\n\t" \
|
||||
STR(PTR)"\t1b, 11b\n\t" \
|
||||
STR(PTR)"\t2b, 11b\n\t" \
|
||||
STR(PTR)"\t3b, 11b\n\t" \
|
||||
STR(PTR)"\t4b, 11b\n\t" \
|
||||
STR(PTR)"\t5b, 11b\n\t" \
|
||||
STR(PTR)"\t6b, 11b\n\t" \
|
||||
STR(PTR)"\t7b, 11b\n\t" \
|
||||
STR(PTR)"\t8b, 11b\n\t" \
|
||||
".previous" \
|
||||
: "=&r" (res) \
|
||||
: "r" (value), "r" (addr), "i" (-EFAULT) \
|
||||
: "memory");
|
||||
#endif /* CONFIG_CPU_MIPSR6 */
|
||||
#endif
|
||||
|
||||
static void emulate_load_store_insn(struct pt_regs *regs,
|
||||
|
|
@ -703,10 +1082,13 @@ static void emulate_load_store_insn(struct pt_regs *regs,
|
|||
break;
|
||||
return;
|
||||
|
||||
#ifndef CONFIG_CPU_MIPSR6
|
||||
/*
|
||||
* COP2 is available to implementor for application specific use.
|
||||
* It's up to applications to register a notifier chain and do
|
||||
* whatever they have to do, including possible sending of signals.
|
||||
*
|
||||
* This instruction has been reallocated in Release 6
|
||||
*/
|
||||
case lwc2_op:
|
||||
cu2_notifier_call_chain(CU2_LWC2_OP, regs);
|
||||
|
|
@ -723,7 +1105,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
|
|||
case sdc2_op:
|
||||
cu2_notifier_call_chain(CU2_SDC2_OP, regs);
|
||||
break;
|
||||
|
||||
#endif
|
||||
default:
|
||||
/*
|
||||
* Pheeee... We encountered an yet unknown instruction or
|
||||
|
|
|
|||
Loading…
Reference in New Issue