drm/i915/gt: Replace hangcheck by heartbeats
Replace sampling the engine state every so often with a periodic heartbeat request to measure the health of an engine. This is coupled with the forced-preemption to allow long running requests to survive so long as they do not block other users. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023133108.21401-5-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
2e0986a58c
commit
058179e72e
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@ -12,6 +12,17 @@ config DRM_I915_USERFAULT_AUTOSUSPEND
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May be 0 to disable the extra delay and solely use the device level
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runtime pm autosuspend delay tunable.
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config DRM_I915_HEARTBEAT_INTERVAL
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int "Interval between heartbeat pulses (ms)"
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default 2500 # milliseconds
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help
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The driver sends a periodic heartbeat down all active engines to
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check the health of the GPU and undertake regular house-keeping of
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internal driver state.
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May be 0 to disable heartbeats and therefore disable automatic GPU
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hang detection.
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config DRM_I915_PREEMPT_TIMEOUT
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int "Preempt timeout (ms, jiffy granularity)"
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default 100 # milliseconds
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@ -87,7 +87,6 @@ gt-y += \
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gt/intel_gt_pm.o \
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gt/intel_gt_pm_irq.o \
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gt/intel_gt_requests.o \
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gt/intel_hangcheck.o \
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gt/intel_llc.o \
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gt/intel_lrc.o \
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gt/intel_rc6.o \
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@ -14863,7 +14863,7 @@ static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
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static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
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{
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struct i915_sched_attr attr = {
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.priority = I915_PRIORITY_DISPLAY,
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.priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
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};
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i915_gem_object_wait_priority(obj, 0, &attr);
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@ -462,6 +462,5 @@ int i915_gem_object_wait(struct drm_i915_gem_object *obj,
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int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
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unsigned int flags,
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const struct i915_sched_attr *attr);
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#define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
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#endif
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@ -76,8 +76,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
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intel_gt_suspend(&i915->gt);
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intel_uc_suspend(&i915->gt.uc);
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cancel_delayed_work_sync(&i915->gt.hangcheck.work);
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i915_gem_drain_freed_objects(i915);
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}
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@ -91,38 +91,6 @@ struct intel_gt;
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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enum intel_engine_hangcheck_action {
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ENGINE_IDLE = 0,
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ENGINE_WAIT,
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ENGINE_ACTIVE_SEQNO,
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ENGINE_ACTIVE_HEAD,
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ENGINE_ACTIVE_SUBUNITS,
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ENGINE_WAIT_KICK,
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ENGINE_DEAD,
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};
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static inline const char *
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hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
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{
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switch (a) {
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case ENGINE_IDLE:
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return "idle";
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case ENGINE_WAIT:
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return "wait";
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case ENGINE_ACTIVE_SEQNO:
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return "active seqno";
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case ENGINE_ACTIVE_HEAD:
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return "active head";
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case ENGINE_ACTIVE_SUBUNITS:
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return "active subunits";
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case ENGINE_WAIT_KICK:
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return "wait kick";
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case ENGINE_DEAD:
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return "dead";
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}
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return "unknown";
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}
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static inline unsigned int
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execlists_num_ports(const struct intel_engine_execlists * const execlists)
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@ -308,6 +308,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
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engine->instance = info->instance;
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__sprint_engine_name(engine);
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engine->props.heartbeat_interval_ms =
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CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
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engine->props.preempt_timeout_ms =
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CONFIG_DRM_I915_PREEMPT_TIMEOUT;
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engine->props.stop_timeout_ms =
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@ -609,7 +611,6 @@ static int intel_engine_setup_common(struct intel_engine_cs *engine)
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intel_engine_init_active(engine, ENGINE_PHYSICAL);
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intel_engine_init_breadcrumbs(engine);
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intel_engine_init_execlists(engine);
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intel_engine_init_hangcheck(engine);
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intel_engine_init_cmd_parser(engine);
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intel_engine_init__pm(engine);
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@ -1470,8 +1471,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
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drm_printf(m, "*** WEDGED ***\n");
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drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
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drm_printf(m, "\tHangcheck: %d ms ago\n",
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jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
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rcu_read_lock();
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rq = READ_ONCE(engine->heartbeat.systole);
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if (rq)
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drm_printf(m, "\tHeartbeat: %d ms ago\n",
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jiffies_to_msecs(jiffies - rq->emitted_jiffies));
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rcu_read_unlock();
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drm_printf(m, "\tReset count: %d (global %d)\n",
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i915_reset_engine_count(error, engine),
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i915_reset_count(error));
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@ -11,6 +11,30 @@
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#include "intel_engine_pm.h"
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#include "intel_engine.h"
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#include "intel_gt.h"
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#include "intel_reset.h"
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/*
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* While the engine is active, we send a periodic pulse along the engine
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* to check on its health and to flush any idle-barriers. If that request
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* is stuck, and we fail to preempt it, we declare the engine hung and
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* issue a reset -- in the hope that restores progress.
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*/
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static bool next_heartbeat(struct intel_engine_cs *engine)
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{
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long delay;
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delay = READ_ONCE(engine->props.heartbeat_interval_ms);
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if (!delay)
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return false;
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delay = msecs_to_jiffies_timeout(delay);
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if (delay >= HZ)
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delay = round_jiffies_up_relative(delay);
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schedule_delayed_work(&engine->heartbeat.work, delay);
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return true;
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}
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static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
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{
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@ -18,6 +42,139 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
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i915_request_add_active_barriers(rq);
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}
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static void show_heartbeat(const struct i915_request *rq,
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struct intel_engine_cs *engine)
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{
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struct drm_printer p = drm_debug_printer("heartbeat");
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intel_engine_dump(engine, &p,
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"%s heartbeat {prio:%d} not ticking\n",
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engine->name,
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rq->sched.attr.priority);
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}
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static void heartbeat(struct work_struct *wrk)
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{
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struct i915_sched_attr attr = {
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.priority = I915_USER_PRIORITY(I915_PRIORITY_MIN),
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};
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struct intel_engine_cs *engine =
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container_of(wrk, typeof(*engine), heartbeat.work.work);
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struct intel_context *ce = engine->kernel_context;
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struct i915_request *rq;
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if (!intel_engine_pm_get_if_awake(engine))
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return;
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rq = engine->heartbeat.systole;
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if (rq && i915_request_completed(rq)) {
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i915_request_put(rq);
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engine->heartbeat.systole = NULL;
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}
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if (intel_gt_is_wedged(engine->gt))
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goto out;
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if (engine->heartbeat.systole) {
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if (engine->schedule &&
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rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
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/*
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* Gradually raise the priority of the heartbeat to
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* give high priority work [which presumably desires
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* low latency and no jitter] the chance to naturally
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* complete before being preempted.
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*/
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attr.priority = I915_PRIORITY_MASK;
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if (rq->sched.attr.priority >= attr.priority)
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attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
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if (rq->sched.attr.priority >= attr.priority)
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attr.priority = I915_PRIORITY_BARRIER;
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local_bh_disable();
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engine->schedule(rq, &attr);
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local_bh_enable();
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} else {
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if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
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show_heartbeat(rq, engine);
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intel_gt_handle_error(engine->gt, engine->mask,
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I915_ERROR_CAPTURE,
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"stopped heartbeat on %s",
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engine->name);
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}
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goto out;
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}
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if (engine->wakeref_serial == engine->serial)
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goto out;
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mutex_lock(&ce->timeline->mutex);
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intel_context_enter(ce);
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rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
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intel_context_exit(ce);
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if (IS_ERR(rq))
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goto unlock;
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idle_pulse(engine, rq);
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if (i915_modparams.enable_hangcheck)
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engine->heartbeat.systole = i915_request_get(rq);
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__i915_request_commit(rq);
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__i915_request_queue(rq, &attr);
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unlock:
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mutex_unlock(&ce->timeline->mutex);
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out:
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if (!next_heartbeat(engine))
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i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
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intel_engine_pm_put(engine);
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}
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void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine)
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{
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if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
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return;
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next_heartbeat(engine);
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}
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void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
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{
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cancel_delayed_work(&engine->heartbeat.work);
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i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
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}
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void intel_engine_init_heartbeat(struct intel_engine_cs *engine)
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{
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INIT_DELAYED_WORK(&engine->heartbeat.work, heartbeat);
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}
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int intel_engine_set_heartbeat(struct intel_engine_cs *engine,
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unsigned long delay)
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{
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int err;
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/* Send one last pulse before to cleanup persistent hogs */
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if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) {
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err = intel_engine_pulse(engine);
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if (err)
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return err;
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}
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WRITE_ONCE(engine->props.heartbeat_interval_ms, delay);
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if (intel_engine_pm_get_if_awake(engine)) {
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if (delay)
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intel_engine_unpark_heartbeat(engine);
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else
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intel_engine_park_heartbeat(engine);
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intel_engine_pm_put(engine);
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}
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return 0;
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}
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int intel_engine_pulse(struct intel_engine_cs *engine)
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{
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struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
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@ -9,6 +9,14 @@
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struct intel_engine_cs;
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void intel_engine_init_heartbeat(struct intel_engine_cs *engine);
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int intel_engine_set_heartbeat(struct intel_engine_cs *engine,
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unsigned long delay);
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void intel_engine_park_heartbeat(struct intel_engine_cs *engine);
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void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);
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int intel_engine_pulse(struct intel_engine_cs *engine);
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int intel_engine_flush_barriers(struct intel_engine_cs *engine);
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@ -7,6 +7,7 @@
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#include "i915_drv.h"
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#include "intel_engine.h"
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#include "intel_engine_heartbeat.h"
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#include "intel_engine_pm.h"
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#include "intel_engine_pool.h"
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#include "intel_gt.h"
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@ -34,7 +35,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
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if (engine->unpark)
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engine->unpark(engine);
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intel_engine_init_hangcheck(engine);
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intel_engine_unpark_heartbeat(engine);
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return 0;
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}
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@ -158,6 +159,7 @@ static int __engine_park(struct intel_wakeref *wf)
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call_idle_barriers(engine); /* cleanup after wedging */
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intel_engine_park_heartbeat(engine);
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intel_engine_disarm_breadcrumbs(engine);
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intel_engine_pool_park(&engine->pool);
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@ -188,6 +190,7 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
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struct intel_runtime_pm *rpm = engine->uncore->rpm;
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intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
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intel_engine_init_heartbeat(engine);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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@ -15,6 +15,7 @@
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#include <linux/rbtree.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "i915_gem.h"
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#include "i915_pmu.h"
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@ -76,14 +77,6 @@ struct intel_instdone {
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u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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};
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struct intel_engine_hangcheck {
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u64 acthd;
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u32 last_ring;
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u32 last_head;
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unsigned long action_timestamp;
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struct intel_instdone instdone;
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};
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struct intel_ring {
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struct kref ref;
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struct i915_vma *vma;
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@ -331,6 +324,11 @@ struct intel_engine_cs {
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intel_engine_mask_t saturated; /* submitting semaphores too late? */
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struct {
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struct delayed_work work;
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struct i915_request *systole;
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} heartbeat;
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unsigned long serial;
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unsigned long wakeref_serial;
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@ -481,8 +479,6 @@ struct intel_engine_cs {
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/* status_notifier: list of callbacks for context-switch changes */
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struct atomic_notifier_head context_status_notifier;
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struct intel_engine_hangcheck hangcheck;
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#define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
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#define I915_ENGINE_SUPPORTS_STATS BIT(1)
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#define I915_ENGINE_HAS_PREEMPTION BIT(2)
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@ -549,6 +545,7 @@ struct intel_engine_cs {
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} stats;
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struct {
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unsigned long heartbeat_interval_ms;
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unsigned long preempt_timeout_ms;
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unsigned long stop_timeout_ms;
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} props;
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@ -22,7 +22,6 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
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INIT_LIST_HEAD(>->closed_vma);
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spin_lock_init(>->closed_lock);
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intel_gt_init_hangcheck(gt);
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intel_gt_init_reset(gt);
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intel_gt_init_requests(gt);
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intel_gt_pm_init_early(gt);
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@ -46,8 +46,6 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
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void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
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void intel_gt_chipset_flush(struct intel_gt *gt);
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void intel_gt_init_hangcheck(struct intel_gt *gt);
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static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
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enum intel_gt_scratch_field field)
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{
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@ -59,6 +57,4 @@ static inline bool intel_gt_is_wedged(struct intel_gt *gt)
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return __intel_reset_failed(>->reset);
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}
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void intel_gt_queue_hangcheck(struct intel_gt *gt);
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#endif /* __INTEL_GT_H__ */
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@ -47,7 +47,6 @@ static int __gt_unpark(struct intel_wakeref *wf)
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i915_pmu_gt_unparked(i915);
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intel_gt_queue_hangcheck(gt);
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intel_gt_unpark_requests(gt);
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return 0;
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@ -27,14 +27,6 @@ struct i915_ggtt;
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struct intel_engine_cs;
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struct intel_uncore;
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struct intel_hangcheck {
|
||||
/* For hangcheck timer */
|
||||
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
|
||||
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
|
||||
|
||||
struct delayed_work work;
|
||||
};
|
||||
|
||||
struct intel_gt {
|
||||
struct drm_i915_private *i915;
|
||||
struct intel_uncore *uncore;
|
||||
|
|
@ -68,7 +60,6 @@ struct intel_gt {
|
|||
struct list_head closed_vma;
|
||||
spinlock_t closed_lock; /* guards the list of closed_vma */
|
||||
|
||||
struct intel_hangcheck hangcheck;
|
||||
struct intel_reset reset;
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1,361 +0,0 @@
|
|||
/*
|
||||
* Copyright © 2016 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "intel_engine.h"
|
||||
#include "intel_gt.h"
|
||||
#include "intel_reset.h"
|
||||
|
||||
struct hangcheck {
|
||||
u64 acthd;
|
||||
u32 ring;
|
||||
u32 head;
|
||||
enum intel_engine_hangcheck_action action;
|
||||
unsigned long action_timestamp;
|
||||
int deadlock;
|
||||
struct intel_instdone instdone;
|
||||
bool wedged:1;
|
||||
bool stalled:1;
|
||||
};
|
||||
|
||||
static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
|
||||
{
|
||||
u32 tmp = current_instdone | *old_instdone;
|
||||
bool unchanged;
|
||||
|
||||
unchanged = tmp == *old_instdone;
|
||||
*old_instdone |= tmp;
|
||||
|
||||
return unchanged;
|
||||
}
|
||||
|
||||
static bool subunits_stuck(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
|
||||
struct intel_instdone instdone;
|
||||
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
|
||||
bool stuck;
|
||||
int slice;
|
||||
int subslice;
|
||||
|
||||
intel_engine_get_instdone(engine, &instdone);
|
||||
|
||||
/* There might be unstable subunit states even when
|
||||
* actual head is not moving. Filter out the unstable ones by
|
||||
* accumulating the undone -> done transitions and only
|
||||
* consider those as progress.
|
||||
*/
|
||||
stuck = instdone_unchanged(instdone.instdone,
|
||||
&accu_instdone->instdone);
|
||||
stuck &= instdone_unchanged(instdone.slice_common,
|
||||
&accu_instdone->slice_common);
|
||||
|
||||
for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
|
||||
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
|
||||
&accu_instdone->sampler[slice][subslice]);
|
||||
stuck &= instdone_unchanged(instdone.row[slice][subslice],
|
||||
&accu_instdone->row[slice][subslice]);
|
||||
}
|
||||
|
||||
return stuck;
|
||||
}
|
||||
|
||||
static enum intel_engine_hangcheck_action
|
||||
head_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
if (acthd != engine->hangcheck.acthd) {
|
||||
|
||||
/* Clear subunit states on head movement */
|
||||
memset(&engine->hangcheck.instdone, 0,
|
||||
sizeof(engine->hangcheck.instdone));
|
||||
|
||||
return ENGINE_ACTIVE_HEAD;
|
||||
}
|
||||
|
||||
if (!subunits_stuck(engine))
|
||||
return ENGINE_ACTIVE_SUBUNITS;
|
||||
|
||||
return ENGINE_DEAD;
|
||||
}
|
||||
|
||||
static enum intel_engine_hangcheck_action
|
||||
engine_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
enum intel_engine_hangcheck_action ha;
|
||||
u32 tmp;
|
||||
|
||||
ha = head_stuck(engine, acthd);
|
||||
if (ha != ENGINE_DEAD)
|
||||
return ha;
|
||||
|
||||
if (IS_GEN(engine->i915, 2))
|
||||
return ENGINE_DEAD;
|
||||
|
||||
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
||||
* If so we can simply poke the RB_WAIT bit
|
||||
* and break the hang. This should work on
|
||||
* all but the second generation chipsets.
|
||||
*/
|
||||
tmp = ENGINE_READ(engine, RING_CTL);
|
||||
if (tmp & RING_WAIT) {
|
||||
intel_gt_handle_error(engine->gt, engine->mask, 0,
|
||||
"stuck wait on %s", engine->name);
|
||||
ENGINE_WRITE(engine, RING_CTL, tmp);
|
||||
return ENGINE_WAIT_KICK;
|
||||
}
|
||||
|
||||
return ENGINE_DEAD;
|
||||
}
|
||||
|
||||
static void hangcheck_load_sample(struct intel_engine_cs *engine,
|
||||
struct hangcheck *hc)
|
||||
{
|
||||
hc->acthd = intel_engine_get_active_head(engine);
|
||||
hc->ring = ENGINE_READ(engine, RING_START);
|
||||
hc->head = ENGINE_READ(engine, RING_HEAD);
|
||||
}
|
||||
|
||||
static void hangcheck_store_sample(struct intel_engine_cs *engine,
|
||||
const struct hangcheck *hc)
|
||||
{
|
||||
engine->hangcheck.acthd = hc->acthd;
|
||||
engine->hangcheck.last_ring = hc->ring;
|
||||
engine->hangcheck.last_head = hc->head;
|
||||
}
|
||||
|
||||
static enum intel_engine_hangcheck_action
|
||||
hangcheck_get_action(struct intel_engine_cs *engine,
|
||||
const struct hangcheck *hc)
|
||||
{
|
||||
if (intel_engine_is_idle(engine))
|
||||
return ENGINE_IDLE;
|
||||
|
||||
if (engine->hangcheck.last_ring != hc->ring)
|
||||
return ENGINE_ACTIVE_SEQNO;
|
||||
|
||||
if (engine->hangcheck.last_head != hc->head)
|
||||
return ENGINE_ACTIVE_SEQNO;
|
||||
|
||||
return engine_stuck(engine, hc->acthd);
|
||||
}
|
||||
|
||||
static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
|
||||
struct hangcheck *hc)
|
||||
{
|
||||
unsigned long timeout = I915_ENGINE_DEAD_TIMEOUT;
|
||||
|
||||
hc->action = hangcheck_get_action(engine, hc);
|
||||
|
||||
/* We always increment the progress
|
||||
* if the engine is busy and still processing
|
||||
* the same request, so that no single request
|
||||
* can run indefinitely (such as a chain of
|
||||
* batches). The only time we do not increment
|
||||
* the hangcheck score on this ring, if this
|
||||
* engine is in a legitimate wait for another
|
||||
* engine. In that case the waiting engine is a
|
||||
* victim and we want to be sure we catch the
|
||||
* right culprit. Then every time we do kick
|
||||
* the ring, make it as a progress as the seqno
|
||||
* advancement might ensure and if not, it
|
||||
* will catch the hanging engine.
|
||||
*/
|
||||
|
||||
switch (hc->action) {
|
||||
case ENGINE_IDLE:
|
||||
case ENGINE_ACTIVE_SEQNO:
|
||||
/* Clear head and subunit states on seqno movement */
|
||||
hc->acthd = 0;
|
||||
|
||||
memset(&engine->hangcheck.instdone, 0,
|
||||
sizeof(engine->hangcheck.instdone));
|
||||
|
||||
/* Intentional fall through */
|
||||
case ENGINE_WAIT_KICK:
|
||||
case ENGINE_WAIT:
|
||||
engine->hangcheck.action_timestamp = jiffies;
|
||||
break;
|
||||
|
||||
case ENGINE_ACTIVE_HEAD:
|
||||
case ENGINE_ACTIVE_SUBUNITS:
|
||||
/*
|
||||
* Seqno stuck with still active engine gets leeway,
|
||||
* in hopes that it is just a long shader.
|
||||
*/
|
||||
timeout = I915_SEQNO_DEAD_TIMEOUT;
|
||||
break;
|
||||
|
||||
case ENGINE_DEAD:
|
||||
break;
|
||||
|
||||
default:
|
||||
MISSING_CASE(hc->action);
|
||||
}
|
||||
|
||||
hc->stalled = time_after(jiffies,
|
||||
engine->hangcheck.action_timestamp + timeout);
|
||||
hc->wedged = time_after(jiffies,
|
||||
engine->hangcheck.action_timestamp +
|
||||
I915_ENGINE_WEDGED_TIMEOUT);
|
||||
}
|
||||
|
||||
static void hangcheck_declare_hang(struct intel_gt *gt,
|
||||
intel_engine_mask_t hung,
|
||||
intel_engine_mask_t stuck)
|
||||
{
|
||||
struct intel_engine_cs *engine;
|
||||
intel_engine_mask_t tmp;
|
||||
char msg[80];
|
||||
int len;
|
||||
|
||||
/* If some rings hung but others were still busy, only
|
||||
* blame the hanging rings in the synopsis.
|
||||
*/
|
||||
if (stuck != hung)
|
||||
hung &= ~stuck;
|
||||
len = scnprintf(msg, sizeof(msg),
|
||||
"%s on ", stuck == hung ? "no progress" : "hang");
|
||||
for_each_engine_masked(engine, gt, hung, tmp)
|
||||
len += scnprintf(msg + len, sizeof(msg) - len,
|
||||
"%s, ", engine->name);
|
||||
msg[len-2] = '\0';
|
||||
|
||||
return intel_gt_handle_error(gt, hung, I915_ERROR_CAPTURE, "%s", msg);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is called when the chip hasn't reported back with completed
|
||||
* batchbuffers in a long time. We keep track per ring seqno progress and
|
||||
* if there are no progress, hangcheck score for that ring is increased.
|
||||
* Further, acthd is inspected to see if the ring is stuck. On stuck case
|
||||
* we kick the ring. If we see no progress on three subsequent calls
|
||||
* we assume chip is wedged and try to fix it by resetting the chip.
|
||||
*/
|
||||
static void hangcheck_elapsed(struct work_struct *work)
|
||||
{
|
||||
struct intel_gt *gt =
|
||||
container_of(work, typeof(*gt), hangcheck.work.work);
|
||||
intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
intel_wakeref_t wakeref;
|
||||
|
||||
if (!i915_modparams.enable_hangcheck)
|
||||
return;
|
||||
|
||||
if (!READ_ONCE(gt->awake))
|
||||
return;
|
||||
|
||||
if (intel_gt_is_wedged(gt))
|
||||
return;
|
||||
|
||||
wakeref = intel_runtime_pm_get_if_in_use(gt->uncore->rpm);
|
||||
if (!wakeref)
|
||||
return;
|
||||
|
||||
/* As enabling the GPU requires fairly extensive mmio access,
|
||||
* periodically arm the mmio checker to see if we are triggering
|
||||
* any invalid access.
|
||||
*/
|
||||
intel_uncore_arm_unclaimed_mmio_detection(gt->uncore);
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
struct hangcheck hc;
|
||||
|
||||
intel_engine_breadcrumbs_irq(engine);
|
||||
|
||||
hangcheck_load_sample(engine, &hc);
|
||||
hangcheck_accumulate_sample(engine, &hc);
|
||||
hangcheck_store_sample(engine, &hc);
|
||||
|
||||
if (hc.stalled) {
|
||||
hung |= engine->mask;
|
||||
if (hc.action != ENGINE_DEAD)
|
||||
stuck |= engine->mask;
|
||||
}
|
||||
|
||||
if (hc.wedged)
|
||||
wedged |= engine->mask;
|
||||
}
|
||||
|
||||
if (GEM_SHOW_DEBUG() && (hung | stuck)) {
|
||||
struct drm_printer p = drm_debug_printer("hangcheck");
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
if (intel_engine_is_idle(engine))
|
||||
continue;
|
||||
|
||||
intel_engine_dump(engine, &p, "%s\n", engine->name);
|
||||
}
|
||||
}
|
||||
|
||||
if (wedged) {
|
||||
dev_err(gt->i915->drm.dev,
|
||||
"GPU recovery timed out,"
|
||||
" cancelling all in-flight rendering.\n");
|
||||
GEM_TRACE_DUMP();
|
||||
intel_gt_set_wedged(gt);
|
||||
}
|
||||
|
||||
if (hung)
|
||||
hangcheck_declare_hang(gt, hung, stuck);
|
||||
|
||||
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
|
||||
|
||||
/* Reset timer in case GPU hangs without another request being added */
|
||||
intel_gt_queue_hangcheck(gt);
|
||||
}
|
||||
|
||||
void intel_gt_queue_hangcheck(struct intel_gt *gt)
|
||||
{
|
||||
unsigned long delay;
|
||||
|
||||
if (unlikely(!i915_modparams.enable_hangcheck))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Don't continually defer the hangcheck so that it is always run at
|
||||
* least once after work has been scheduled on any ring. Otherwise,
|
||||
* we will ignore a hung ring if a second ring is kept busy.
|
||||
*/
|
||||
|
||||
delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
|
||||
queue_delayed_work(system_long_wq, >->hangcheck.work, delay);
|
||||
}
|
||||
|
||||
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
||||
{
|
||||
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
||||
engine->hangcheck.action_timestamp = jiffies;
|
||||
}
|
||||
|
||||
void intel_gt_init_hangcheck(struct intel_gt *gt)
|
||||
{
|
||||
INIT_DELAYED_WORK(>->hangcheck.work, hangcheck_elapsed);
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
||||
#include "selftest_hangcheck.c"
|
||||
#endif
|
||||
|
|
@ -1024,8 +1024,6 @@ void intel_gt_reset(struct intel_gt *gt,
|
|||
if (ret)
|
||||
goto taint;
|
||||
|
||||
intel_gt_queue_hangcheck(gt);
|
||||
|
||||
finish:
|
||||
reset_finish(gt, awake);
|
||||
unlock:
|
||||
|
|
@ -1353,4 +1351,5 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
|
|||
|
||||
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
||||
#include "selftest_reset.c"
|
||||
#include "selftest_hangcheck.c"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* Copyright © 2018 Intel Corporation
|
||||
*/
|
||||
|
||||
#include <linux/sort.h>
|
||||
|
||||
#include "i915_drv.h"
|
||||
|
||||
#include "intel_gt_requests.h"
|
||||
|
|
@ -150,11 +152,180 @@ static int live_idle_pulse(void *arg)
|
|||
return err;
|
||||
}
|
||||
|
||||
static int cmp_u32(const void *_a, const void *_b)
|
||||
{
|
||||
const u32 *a = _a, *b = _b;
|
||||
|
||||
return *a - *b;
|
||||
}
|
||||
|
||||
static int __live_heartbeat_fast(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct intel_context *ce;
|
||||
struct i915_request *rq;
|
||||
ktime_t t0, t1;
|
||||
u32 times[5];
|
||||
int err;
|
||||
int i;
|
||||
|
||||
ce = intel_context_create(engine->kernel_context->gem_context,
|
||||
engine);
|
||||
if (IS_ERR(ce))
|
||||
return PTR_ERR(ce);
|
||||
|
||||
intel_engine_pm_get(engine);
|
||||
|
||||
err = intel_engine_set_heartbeat(engine, 1);
|
||||
if (err)
|
||||
goto err_pm;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(times); i++) {
|
||||
/* Manufacture a tick */
|
||||
do {
|
||||
while (READ_ONCE(engine->heartbeat.systole))
|
||||
flush_delayed_work(&engine->heartbeat.work);
|
||||
|
||||
engine->serial++; /* quick, pretend we are not idle! */
|
||||
flush_delayed_work(&engine->heartbeat.work);
|
||||
if (!delayed_work_pending(&engine->heartbeat.work)) {
|
||||
pr_err("%s: heartbeat did not start\n",
|
||||
engine->name);
|
||||
err = -EINVAL;
|
||||
goto err_pm;
|
||||
}
|
||||
|
||||
rcu_read_lock();
|
||||
rq = READ_ONCE(engine->heartbeat.systole);
|
||||
if (rq)
|
||||
rq = i915_request_get_rcu(rq);
|
||||
rcu_read_unlock();
|
||||
} while (!rq);
|
||||
|
||||
t0 = ktime_get();
|
||||
while (rq == READ_ONCE(engine->heartbeat.systole))
|
||||
yield(); /* work is on the local cpu! */
|
||||
t1 = ktime_get();
|
||||
|
||||
i915_request_put(rq);
|
||||
times[i] = ktime_us_delta(t1, t0);
|
||||
}
|
||||
|
||||
sort(times, ARRAY_SIZE(times), sizeof(times[0]), cmp_u32, NULL);
|
||||
|
||||
pr_info("%s: Heartbeat delay: %uus [%u, %u]\n",
|
||||
engine->name,
|
||||
times[ARRAY_SIZE(times) / 2],
|
||||
times[0],
|
||||
times[ARRAY_SIZE(times) - 1]);
|
||||
|
||||
/* Min work delay is 2 * 2 (worst), +1 for scheduling, +1 for slack */
|
||||
if (times[ARRAY_SIZE(times) / 2] > jiffies_to_usecs(6)) {
|
||||
pr_err("%s: Heartbeat delay was %uus, expected less than %dus\n",
|
||||
engine->name,
|
||||
times[ARRAY_SIZE(times) / 2],
|
||||
jiffies_to_usecs(6));
|
||||
err = -EINVAL;
|
||||
}
|
||||
|
||||
intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL);
|
||||
err_pm:
|
||||
intel_engine_pm_put(engine);
|
||||
intel_context_put(ce);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int live_heartbeat_fast(void *arg)
|
||||
{
|
||||
struct intel_gt *gt = arg;
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
int err;
|
||||
|
||||
/* Check that the heartbeat ticks at the desired rate. */
|
||||
if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
|
||||
return 0;
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
err = __live_heartbeat_fast(engine);
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __live_heartbeat_off(struct intel_engine_cs *engine)
|
||||
{
|
||||
int err;
|
||||
|
||||
intel_engine_pm_get(engine);
|
||||
|
||||
engine->serial++;
|
||||
flush_delayed_work(&engine->heartbeat.work);
|
||||
if (!delayed_work_pending(&engine->heartbeat.work)) {
|
||||
pr_err("%s: heartbeat not running\n",
|
||||
engine->name);
|
||||
err = -EINVAL;
|
||||
goto err_pm;
|
||||
}
|
||||
|
||||
err = intel_engine_set_heartbeat(engine, 0);
|
||||
if (err)
|
||||
goto err_pm;
|
||||
|
||||
engine->serial++;
|
||||
flush_delayed_work(&engine->heartbeat.work);
|
||||
if (delayed_work_pending(&engine->heartbeat.work)) {
|
||||
pr_err("%s: heartbeat still running\n",
|
||||
engine->name);
|
||||
err = -EINVAL;
|
||||
goto err_beat;
|
||||
}
|
||||
|
||||
if (READ_ONCE(engine->heartbeat.systole)) {
|
||||
pr_err("%s: heartbeat still allocated\n",
|
||||
engine->name);
|
||||
err = -EINVAL;
|
||||
goto err_beat;
|
||||
}
|
||||
|
||||
err_beat:
|
||||
intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL);
|
||||
err_pm:
|
||||
intel_engine_pm_put(engine);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int live_heartbeat_off(void *arg)
|
||||
{
|
||||
struct intel_gt *gt = arg;
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
int err;
|
||||
|
||||
/* Check that we can turn off heartbeat and not interrupt VIP */
|
||||
if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
|
||||
return 0;
|
||||
|
||||
for_each_engine(engine, gt, id) {
|
||||
if (!intel_engine_has_preemption(engine))
|
||||
continue;
|
||||
|
||||
err = __live_heartbeat_off(engine);
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
|
||||
{
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(live_idle_flush),
|
||||
SUBTEST(live_idle_pulse),
|
||||
SUBTEST(live_heartbeat_fast),
|
||||
SUBTEST(live_heartbeat_off),
|
||||
};
|
||||
int saved_hangcheck;
|
||||
int err;
|
||||
|
|
|
|||
|
|
@ -1686,7 +1686,6 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
|
|||
};
|
||||
struct intel_gt *gt = &i915->gt;
|
||||
intel_wakeref_t wakeref;
|
||||
bool saved_hangcheck;
|
||||
int err;
|
||||
|
||||
if (!intel_has_gpu_reset(gt))
|
||||
|
|
@ -1696,12 +1695,9 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
|
|||
return -EIO; /* we're long past hope of a successful reset */
|
||||
|
||||
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
|
||||
saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
|
||||
drain_delayed_work(>->hangcheck.work); /* flush param */
|
||||
|
||||
err = intel_gt_live_subtests(tests, gt);
|
||||
|
||||
i915_modparams.enable_hangcheck = saved_hangcheck;
|
||||
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
|
||||
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -1011,92 +1011,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void i915_instdone_info(struct drm_i915_private *dev_priv,
|
||||
struct seq_file *m,
|
||||
struct intel_instdone *instdone)
|
||||
{
|
||||
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
|
||||
int slice;
|
||||
int subslice;
|
||||
|
||||
seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
|
||||
instdone->instdone);
|
||||
|
||||
if (INTEL_GEN(dev_priv) <= 3)
|
||||
return;
|
||||
|
||||
seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
|
||||
instdone->slice_common);
|
||||
|
||||
if (INTEL_GEN(dev_priv) <= 6)
|
||||
return;
|
||||
|
||||
for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
|
||||
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
|
||||
slice, subslice, instdone->sampler[slice][subslice]);
|
||||
|
||||
for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
|
||||
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
|
||||
slice, subslice, instdone->row[slice][subslice]);
|
||||
}
|
||||
|
||||
static int i915_hangcheck_info(struct seq_file *m, void *unused)
|
||||
{
|
||||
struct drm_i915_private *i915 = node_to_i915(m->private);
|
||||
struct intel_gt *gt = &i915->gt;
|
||||
struct intel_engine_cs *engine;
|
||||
intel_wakeref_t wakeref;
|
||||
enum intel_engine_id id;
|
||||
|
||||
seq_printf(m, "Reset flags: %lx\n", gt->reset.flags);
|
||||
if (test_bit(I915_WEDGED, >->reset.flags))
|
||||
seq_puts(m, "\tWedged\n");
|
||||
if (test_bit(I915_RESET_BACKOFF, >->reset.flags))
|
||||
seq_puts(m, "\tDevice (global) reset in progress\n");
|
||||
|
||||
if (!i915_modparams.enable_hangcheck) {
|
||||
seq_puts(m, "Hangcheck disabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (timer_pending(>->hangcheck.work.timer))
|
||||
seq_printf(m, "Hangcheck active, timer fires in %dms\n",
|
||||
jiffies_to_msecs(gt->hangcheck.work.timer.expires -
|
||||
jiffies));
|
||||
else if (delayed_work_pending(>->hangcheck.work))
|
||||
seq_puts(m, "Hangcheck active, work pending\n");
|
||||
else
|
||||
seq_puts(m, "Hangcheck inactive\n");
|
||||
|
||||
seq_printf(m, "GT active? %s\n", yesno(gt->awake));
|
||||
|
||||
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
|
||||
for_each_engine(engine, i915, id) {
|
||||
struct intel_instdone instdone;
|
||||
|
||||
seq_printf(m, "%s: %d ms ago\n",
|
||||
engine->name,
|
||||
jiffies_to_msecs(jiffies -
|
||||
engine->hangcheck.action_timestamp));
|
||||
|
||||
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
|
||||
(long long)engine->hangcheck.acthd,
|
||||
intel_engine_get_active_head(engine));
|
||||
|
||||
intel_engine_get_instdone(engine, &instdone);
|
||||
|
||||
seq_puts(m, "\tinstdone read =\n");
|
||||
i915_instdone_info(i915, m, &instdone);
|
||||
|
||||
seq_puts(m, "\tinstdone accu =\n");
|
||||
i915_instdone_info(i915, m,
|
||||
&engine->hangcheck.instdone);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ironlake_drpc_info(struct seq_file *m)
|
||||
{
|
||||
struct drm_i915_private *i915 = node_to_i915(m->private);
|
||||
|
|
@ -4363,7 +4277,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
|
|||
{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
|
||||
{"i915_huc_load_status", i915_huc_load_status_info, 0},
|
||||
{"i915_frequency_info", i915_frequency_info, 0},
|
||||
{"i915_hangcheck_info", i915_hangcheck_info, 0},
|
||||
{"i915_drpc_info", i915_drpc_info, 0},
|
||||
{"i915_ring_freq_table", i915_ring_freq_table, 0},
|
||||
{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
|
||||
|
|
|
|||
|
|
@ -1548,10 +1548,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
|
|||
|
||||
i915_driver_modeset_remove(i915);
|
||||
|
||||
/* Free error state after interrupts are fully disabled. */
|
||||
cancel_delayed_work_sync(&i915->gt.hangcheck.work);
|
||||
i915_reset_error_state(i915);
|
||||
|
||||
i915_gem_driver_remove(i915);
|
||||
|
||||
intel_power_domains_driver_remove(i915);
|
||||
|
|
|
|||
|
|
@ -1846,7 +1846,6 @@ void i915_driver_remove(struct drm_i915_private *i915);
|
|||
int i915_resume_switcheroo(struct drm_i915_private *i915);
|
||||
int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
|
||||
|
||||
void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
|
||||
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
|
||||
|
||||
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
|
||||
|
|
|
|||
|
|
@ -534,10 +534,6 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
|
|||
}
|
||||
err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
|
||||
err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
|
||||
err_printf(m, " hangcheck timestamp: %dms (%lu%s)\n",
|
||||
jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
|
||||
ee->hangcheck_timestamp,
|
||||
ee->hangcheck_timestamp == epoch ? "; epoch" : "");
|
||||
err_printf(m, " engine reset count: %u\n", ee->reset_count);
|
||||
|
||||
for (n = 0; n < ee->num_ports; n++) {
|
||||
|
|
@ -679,11 +675,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
|
|||
ts = ktime_to_timespec64(error->uptime);
|
||||
err_printf(m, "Uptime: %lld s %ld us\n",
|
||||
(s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
|
||||
err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
|
||||
err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
|
||||
error->capture,
|
||||
jiffies_to_msecs(jiffies - error->capture),
|
||||
jiffies_to_msecs(error->capture - error->epoch));
|
||||
err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
|
||||
error->capture, jiffies_to_msecs(jiffies - error->capture));
|
||||
|
||||
for (ee = error->engine; ee; ee = ee->next)
|
||||
err_printf(m, "Active process (on ring %s): %s [%d]\n",
|
||||
|
|
@ -742,7 +735,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
|
|||
err_printf(m, "GTT_CACHE_EN: 0x%08x\n", error->gtt_cache);
|
||||
|
||||
for (ee = error->engine; ee; ee = ee->next)
|
||||
error_print_engine(m, ee, error->epoch);
|
||||
error_print_engine(m, ee, error->capture);
|
||||
|
||||
for (ee = error->engine; ee; ee = ee->next) {
|
||||
const struct drm_i915_error_object *obj;
|
||||
|
|
@ -770,7 +763,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
|
|||
for (j = 0; j < ee->num_requests; j++)
|
||||
error_print_request(m, " ",
|
||||
&ee->requests[j],
|
||||
error->epoch);
|
||||
error->capture);
|
||||
}
|
||||
|
||||
print_error_obj(m, ee->engine, "ringbuffer", ee->ringbuffer);
|
||||
|
|
@ -1144,8 +1137,6 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
|
|||
}
|
||||
|
||||
ee->idle = intel_engine_is_idle(engine);
|
||||
if (!ee->idle)
|
||||
ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
|
||||
ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
|
||||
engine);
|
||||
|
||||
|
|
@ -1657,20 +1648,6 @@ static void capture_params(struct i915_gpu_state *error)
|
|||
i915_params_copy(&error->params, &i915_modparams);
|
||||
}
|
||||
|
||||
static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
|
||||
{
|
||||
const struct drm_i915_error_engine *ee;
|
||||
unsigned long epoch = error->capture;
|
||||
|
||||
for (ee = error->engine; ee; ee = ee->next) {
|
||||
if (ee->hangcheck_timestamp &&
|
||||
time_before(ee->hangcheck_timestamp, epoch))
|
||||
epoch = ee->hangcheck_timestamp;
|
||||
}
|
||||
|
||||
return epoch;
|
||||
}
|
||||
|
||||
static void capture_finish(struct i915_gpu_state *error)
|
||||
{
|
||||
struct i915_ggtt *ggtt = &error->i915->ggtt;
|
||||
|
|
@ -1722,8 +1699,6 @@ i915_capture_gpu_state(struct drm_i915_private *i915)
|
|||
error->overlay = intel_overlay_capture_error_state(i915);
|
||||
error->display = intel_display_capture_error_state(i915);
|
||||
|
||||
error->epoch = capture_find_epoch(error);
|
||||
|
||||
capture_finish(error);
|
||||
compress_fini(&compress);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ struct i915_gpu_state {
|
|||
ktime_t boottime;
|
||||
ktime_t uptime;
|
||||
unsigned long capture;
|
||||
unsigned long epoch;
|
||||
|
||||
struct drm_i915_private *i915;
|
||||
|
||||
|
|
@ -86,7 +85,6 @@ struct i915_gpu_state {
|
|||
|
||||
/* Software tracked state */
|
||||
bool idle;
|
||||
unsigned long hangcheck_timestamp;
|
||||
int num_requests;
|
||||
u32 reset_count;
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,12 @@ enum {
|
|||
I915_PRIORITY_MIN = I915_CONTEXT_MIN_USER_PRIORITY - 1,
|
||||
I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY,
|
||||
I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1,
|
||||
|
||||
/* A preemptive pulse used to monitor the health of each engine */
|
||||
I915_PRIORITY_HEARTBEAT,
|
||||
|
||||
/* Interactive workload, scheduled for immediate pageflipping */
|
||||
I915_PRIORITY_DISPLAY,
|
||||
};
|
||||
|
||||
#define I915_USER_PRIORITY_SHIFT 2
|
||||
|
|
|
|||
Loading…
Reference in New Issue