More Qualcomm ARM64 DTS changes for v6.5
This introduces support for the Qualcomm SDX75 platform, with the IDP reference board. On IPQ5332 the RDP474 board is added and on IPQ9574 the RDP454 is introduced. On SC8280XP, and hence Lenovo ThinkPad X13s, GPU support is added. For QDU1000, SDM845, SM670, SC8180X, SM6350 and SM8550 the RSC is added to the CPU cluster power-domain to flush sleep & wake votes as the cluster goes down. On IPQ5332 additional reserved-memory regions to improve post mortem debugging. UART1 is added. The MI01.2 board is renamed RDP441 and the RDP474 is added. On IPQ8074 critical thermal trip points are defined. As with IPQ5332 additional reserved-memory regions are used to improve post mortem debugging. Thermal sensors (tsens) are added and zones defined. The crypto engine is added, and support for the RDP454 board is added. Across MSM8916 and MSM8939 pinctrl state definitions are cleaned up and the purpose of msm8939-pm8916 is documented. MSM8939 has regulator definitions cleaned up, following to the previous effort on MSM8916. CPU Bus Fabric scaling support is added to MSM8996 Pro. On QCM2290 CPU idle states are added. For QDU1000 SDHCI is introduced and enabled on the IDP to gain eMMC support. IMEM and PIL information regions are defined for improved post mortem debugging. The Qualcomm Robotics RB2 kit gets its on-board buttons described. A few fixes are introduced for the newly merged SC8180X, in particluar the DisplayPort blocks are moved to the MMCX power domain to avoid power being reduced prematurely during boot. The SC8280XP GPU is added and enabled for the Lenovo Thinkpad X13s, and resets for the soundwire controllers are added. The OUI is specified for ethernet phys on SA8540P Ride platform, to avoid reset issues. Charger description is added to the PMI8998 PMIC and enabled across OnePlus 6/6T, SHIFT SHIFT6mq and Xiaomi Pocophone F1. On SM6350 CPU idle states and UART1 are added. And SM6375 gains GPU clock controller and IOMMU definitions. The Fairphone FP4 gains Bluetooth support. SM8150 is transitioned to use 2 interconnect-cells, and the USB interconnect path is described to ensure buses are adequately voted for. The same changes are done for SM8250, and the resolution of the static framebuffer on Sony Xperia 1 II and 5 II are corrected. The USB bus paths are also added to SM8350, SM8450 and SM8550. On SM8550 DisplayPort nodes are added, as is the PWM controller for driving the notification LED and the RTC is enabled. For the MTP and QRD boards, the soundcard and audio codecs are defined. A Tegra change, related to LP855X binding changes, was accidentally picked up and dropped again later. A number of DeviceTree fixes identified through validation was introduced as well. Additionally a few nodes got their default status changed to avoid unnecessarily having to enable them (e.g. the mdp/dpu node). -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmSLOjsVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FlyUP/0PZFIRutqnwwr/daOZAhDgw6pQW jseUFIUb9yKan8KJZcHOf38xxqfj/bllQQNIQeM8qw03e7LJf/Mcteg3FYNgxD9m vAWdQby2ZBcAYy3Qxjc3H+cb2fPV8yEJZ4JX/yOuLPfx9zE8HMoT8M9JBHZlZc8T 0fzgVxqRz1wt5Qjzv+BsWg4GUiTARtRbYxDVzdFZFDF6f7Xcpdsq+HaImJdYisXh m/2lQ34rDBTVOMN6Og5U7lGjfCyk6hn3k0OoSpObLRBNV34JH6ViDVhmNbFWKNNS QGFDAEa+jjQDrEo2cUHiHfnlKzcQpheLoco7MNkzDwy/8Rd3/k3ndj/+oCpgGea5 VFTb0LygJPQnHfggzpxc+v2pBfoocEUvKrI+sluXeNnLua+jvlLz6Z8Wm6mVaBZv hzw4NqaXHRtzqgjo/37t7Hwns+uyd+rg/gjh8xfdu65/kVZiTstK1BGVCoKMs1LD J0UcQGaevfBH9+EYNcKly5qjEMhsUxwn4i7oyjerdQ7Wt4nwzPqfs7zv513Ns5bO eLG49FsCZjzvAn4AC3R1POPVrP2RBg/zeBzL/34gkgBLr/TR1k1zyPWxovb6Tuq9 8R3T4XBA1kwh1c7R5av1033dyvW4N8y6vp9z+kExuPz4qQ+SsWKoXAeM2budkTQ/ c3oBU6U+BH9oCvSV =Fga/ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSEgoACgkQYKtH/8kJ UifYRg//Uu6CMkGFJCfMVNS8Z0lykAW3FtEupzi+lWVP+2i+QsR8FXTZ3EumyBA6 QoRX1FtEKtRdJatMUgWlCbv8newKiII9fwKrV/EK7u/CTC79zX9ak3DonxXu7Z2i a6dzH5GVnHfVe7BTQdJuOylxKneMNNECmnkYYUWry1LES1zLhUZy67GsdbDSCxpF evzT8ly6NLSSJOJKXlcmwzcGMXhi7HrCdvsZhPdJZ1cN8c/tfrj+S8kmHxs5Qw3B TOjFi14w2CA/duvwQLV+0KIuHc/Vn8oYI0NnD96aahlZA+QFMk1hsdeETtXL6guf S4FKB+PNVtFnMCMq25xsTOaqEKjse8+xBgTN9TAvB67TJUQ3J2zibn1jjaGjtej7 w2ry8FC/pgSFbs9KftAL7mDFCICo7qyOhpfuuG+s+ti1m7h5Fon2a+UKc0T0m80w qR1YXohi6rzXTlcV92m2CRZIvSBPf1UQAnFqyjZBIvePpD8/TqYs2M+IIM0dmaBC Xs+n+3ORIte7hws5BodXaWwsi0NTFm8rQaeK94Cj100kWMxrKZS5JIIdZ/Dy0rRk LXWKj1W4h6rrwM34r5oeyc0k9pYoc7coDItEqu8VyKz7pj9rjcG8B+lqdp6QjNK+ +gNnVF4UmEbRpG6EZm9uC9IshiIQp/8DhO/lRZMb37v1YEB6/mg= =ThxV -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt More Qualcomm ARM64 DTS changes for v6.5 This introduces support for the Qualcomm SDX75 platform, with the IDP reference board. On IPQ5332 the RDP474 board is added and on IPQ9574 the RDP454 is introduced. On SC8280XP, and hence Lenovo ThinkPad X13s, GPU support is added. For QDU1000, SDM845, SM670, SC8180X, SM6350 and SM8550 the RSC is added to the CPU cluster power-domain to flush sleep & wake votes as the cluster goes down. On IPQ5332 additional reserved-memory regions to improve post mortem debugging. UART1 is added. The MI01.2 board is renamed RDP441 and the RDP474 is added. On IPQ8074 critical thermal trip points are defined. As with IPQ5332 additional reserved-memory regions are used to improve post mortem debugging. Thermal sensors (tsens) are added and zones defined. The crypto engine is added, and support for the RDP454 board is added. Across MSM8916 and MSM8939 pinctrl state definitions are cleaned up and the purpose of msm8939-pm8916 is documented. MSM8939 has regulator definitions cleaned up, following to the previous effort on MSM8916. CPU Bus Fabric scaling support is added to MSM8996 Pro. On QCM2290 CPU idle states are added. For QDU1000 SDHCI is introduced and enabled on the IDP to gain eMMC support. IMEM and PIL information regions are defined for improved post mortem debugging. The Qualcomm Robotics RB2 kit gets its on-board buttons described. A few fixes are introduced for the newly merged SC8180X, in particluar the DisplayPort blocks are moved to the MMCX power domain to avoid power being reduced prematurely during boot. The SC8280XP GPU is added and enabled for the Lenovo Thinkpad X13s, and resets for the soundwire controllers are added. The OUI is specified for ethernet phys on SA8540P Ride platform, to avoid reset issues. Charger description is added to the PMI8998 PMIC and enabled across OnePlus 6/6T, SHIFT SHIFT6mq and Xiaomi Pocophone F1. On SM6350 CPU idle states and UART1 are added. And SM6375 gains GPU clock controller and IOMMU definitions. The Fairphone FP4 gains Bluetooth support. SM8150 is transitioned to use 2 interconnect-cells, and the USB interconnect path is described to ensure buses are adequately voted for. The same changes are done for SM8250, and the resolution of the static framebuffer on Sony Xperia 1 II and 5 II are corrected. The USB bus paths are also added to SM8350, SM8450 and SM8550. On SM8550 DisplayPort nodes are added, as is the PWM controller for driving the notification LED and the RTC is enabled. For the MTP and QRD boards, the soundcard and audio codecs are defined. A Tegra change, related to LP855X binding changes, was accidentally picked up and dropped again later. A number of DeviceTree fixes identified through validation was introduced as well. Additionally a few nodes got their default status changed to avoid unnecessarily having to enable them (e.g. the mdp/dpu node). * tag 'qcom-arm64-for-6.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (94 commits) Revert "arm64: dts: adapt to LP855X bindings changes" arm64: dts: qcom: sc8280xp: Enable GPU related nodes arm64: dts: qcom: sc8280xp: Add GPU related nodes arm64: dts: qcom: msm8939-pm8916: Mark always-on regulators arm64: dts: qcom: msm8939: Define regulator constraints next to usage arm64: dts: qcom: msm8939-pm8916: Clarify purpose arm64: dts: qcom: msm8939: Fix regulator constraints arm64: dts: qcom: msm8939-sony-tulip: Allow disabling pm8916_l6 arm64: dts: qcom: msm8939-sony-tulip: Fix l10-l12 regulator voltages arm64: dts: qcom: msm8939: Disable lpass_codec by default arm64: dts: qcom: msm8939-pm8916: Add missing pm8916_codec supplies arm64: dts: qcom: qrb4210-rb2: Enable on-board buttons arm64: dts: qcom: msm8916: Drop msm8916-pins.dtsi arm64: dts: qcom: msm8916/39: Rename wcnss pinctrl arm64: dts: qcom: msm8916/39: Cleanup audio pinctrl arm64: dts: qcom: apq8016-sbc: Drop unneeded MCLK pinctrl arm64: dts: qcom: msm8916/39: Consolidate SDC pinctrl arm64: dts: qcom: msm8916/39: Fix SD card detect pinctrl arm64: dts: qcom: msm8996: rename labels for HDMI nodes arm64: dts: qcom: sm8250: rename labels for DSI nodes ... Link: https://lore.kernel.org/r/20230615162043.1461624-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
055fdcac93
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@ -70,6 +70,7 @@ description: |
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sdm845
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sdx55
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sdx65
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sdx75
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sm4250
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sm6115
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sm6115p
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@ -90,9 +91,11 @@ description: |
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ap-al02-c6
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ap-al02-c7
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ap-al02-c8
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ap-al02-c9
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ap-mi01.2
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ap-mi01.3
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ap-mi01.6
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ap-mi01.9
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cdp
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cp01-c1
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dragonboard
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@ -196,6 +199,7 @@ properties:
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- items:
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- enum:
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- qcom,msm8960-cdp
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- samsung,expressatt
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- const: qcom,msm8960
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- items:
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@ -340,6 +344,7 @@ properties:
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- qcom,ipq5332-ap-mi01.2
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- qcom,ipq5332-ap-mi01.3
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- qcom,ipq5332-ap-mi01.6
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- qcom,ipq5332-ap-mi01.9
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- const: qcom,ipq5332
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- items:
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@ -361,6 +366,7 @@ properties:
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- qcom,ipq9574-ap-al02-c6
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- qcom,ipq9574-ap-al02-c7
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- qcom,ipq9574-ap-al02-c8
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- qcom,ipq9574-ap-al02-c9
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- const: qcom,ipq9574
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- description: Sierra Wireless MangOH Green with WP8548 Module
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@ -828,6 +834,11 @@ properties:
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- qcom,sdx65-mtp
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- const: qcom,sdx65
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- items:
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- enum:
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- qcom,sdx75-idp
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- const: qcom,sdx75
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- items:
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- enum:
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- qcom,ipq6018-cp01
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@ -1056,6 +1067,7 @@ allOf:
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- qcom,sdm845
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- qcom,sdx55
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- qcom,sdx65
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- qcom,sdx75
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- qcom,sm4250
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- qcom,sm6115
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- qcom,sm6125
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@ -0,0 +1,60 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
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maintainers:
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- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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description: |
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Qualcomm LPASS core and audio clock control module provides the clocks,
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and reset on SC8280XP.
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See also::
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include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-lpassaudiocc
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- qcom,sc8280xp-lpasscc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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lpass_audiocc: clock-controller@32a9000 {
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compatible = "qcom,sc8280xp-lpassaudiocc";
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reg = <0x032a9000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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lpasscc: clock-controller@33e0000 {
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compatible = "qcom,sc8280xp-lpasscc";
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reg = <0x033e0000 0x12000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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@ -0,0 +1,65 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on SDX75
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maintainers:
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- Imran Shaik <quic_imrashai@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on SDX75
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See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
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properties:
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compatible:
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const: qcom,sdx75-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: EMAC0 sgmiiphy mac rclk source
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- description: EMAC0 sgmiiphy mac tclk source
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- description: EMAC0 sgmiiphy rclk source
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- description: EMAC0 sgmiiphy tclk source
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- description: EMAC1 sgmiiphy mac rclk source
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- description: EMAC1 sgmiiphy mac tclk source
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- description: EMAC1 sgmiiphy rclk source
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- description: EMAC1 sgmiiphy tclk source
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- description: PCIE20 phy aux clock source
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- description: PCIE_1 Pipe clock source
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- description: PCIE_2 Pipe clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@80000 {
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compatible = "qcom,sdx75-gcc";
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reg = <0x80000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
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<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
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<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
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<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
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<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -4,9 +4,10 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
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@ -15,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
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@ -182,6 +184,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
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|
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@ -370,18 +370,14 @@
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&sdhc_1 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
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pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
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};
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&sdhc_2 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
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pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
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pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
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cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
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};
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@ -389,8 +385,8 @@
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&sound {
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status = "okay";
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pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
|
||||
pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
|
||||
pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
|
||||
pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
model = "DB410c";
|
||||
audio-routing =
|
||||
|
|
@ -642,6 +638,13 @@
|
|||
"USR_LED_2_CTRL", /* GPIO 120 */
|
||||
"SB_HS_ID";
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tlmm_leds: tlmm-leds-state {
|
||||
pins = "gpio21", "gpio120";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -135,6 +135,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&lpass_codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -154,108 +158,7 @@
|
|||
"PM_GPIO4";
|
||||
};
|
||||
|
||||
&smd_rpm_regulators {
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
pm8916_s3: s3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
pm8916_s4: s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
};
|
||||
|
||||
/* l1 is fixed to 1225000, but not connected in schematic */
|
||||
|
||||
pm8916_l2: l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
pm8916_l4: l4 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
};
|
||||
|
||||
pm8916_l5: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l6: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l7: l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l8: l8 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
pm8916_l9: l9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l10: l10 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l11: l11 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
pm8916_l12: l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
pm8916_l13: l13 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
|
||||
pm8916_l14: l14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l15: l15 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l16: l16 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l17: l17 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
pm8916_l18: l18 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_default_state>;
|
||||
pinctrl-1 = <&sdc1_sleep_state>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -263,8 +166,8 @@
|
|||
model = "apq8039-square-sndcard";
|
||||
audio-routing = "AMIC2", "MIC BIAS Internal2";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cdc_pdm_lines_default>;
|
||||
pinctrl-1 = <&cdc_pdm_lines_sleep>;
|
||||
pinctrl-0 = <&cdc_pdm_default>;
|
||||
pinctrl-1 = <&cdc_pdm_sleep>;
|
||||
|
||||
internal-codec-playback-dai-link {
|
||||
link-name = "WCD";
|
||||
|
|
|
|||
|
|
@ -208,25 +208,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
|
||||
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
|
||||
|
||||
core-vdda-supply = <&vreg_l12a_1p8>;
|
||||
core-vcc-supply = <&vreg_s4a_1p8>;
|
||||
};
|
||||
|
||||
&hdmi_phy {
|
||||
status = "okay";
|
||||
|
||||
vddio-supply = <&vreg_l12a_1p8>;
|
||||
vcca-supply = <&vreg_l28a_0p925>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
&hsusb_phy1 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -251,6 +232,25 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_hdmi {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>;
|
||||
pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>;
|
||||
|
||||
core-vdda-supply = <&vreg_l12a_1p8>;
|
||||
core-vcc-supply = <&vreg_s4a_1p8>;
|
||||
};
|
||||
|
||||
&mdss_hdmi_phy {
|
||||
status = "okay";
|
||||
|
||||
vddio-supply = <&vreg_l12a_1p8>;
|
||||
vcca-supply = <&vreg_l28a_0p925>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
&mmcc {
|
||||
vdd-gfx-supply = <&vdd_gfx>;
|
||||
};
|
||||
|
|
@ -433,28 +433,28 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
hdmi_hpd_active: hdmi-hpd-active-state {
|
||||
mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state {
|
||||
pins = "gpio34";
|
||||
function = "hdmi_hot";
|
||||
bias-pull-down;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
hdmi_hpd_suspend: hdmi-hpd-suspend-state {
|
||||
mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state {
|
||||
pins = "gpio34";
|
||||
function = "hdmi_hot";
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
hdmi_ddc_active: hdmi-ddc-active-state {
|
||||
mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state {
|
||||
pins = "gpio32", "gpio33";
|
||||
function = "hdmi_ddc";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hdmi_ddc_suspend: hdmi-ddc-suspend-state {
|
||||
mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state {
|
||||
pins = "gpio32", "gpio33";
|
||||
function = "hdmi_ddc";
|
||||
drive-strength = <2>;
|
||||
|
|
@ -1043,7 +1043,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-dai-link {
|
||||
mdss_hdmi-dai-link {
|
||||
link-name = "HDMI";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai HDMI_RX>;
|
||||
|
|
@ -1054,7 +1054,7 @@
|
|||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&hdmi 0>;
|
||||
sound-dai = <&mdss_hdmi 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -92,18 +92,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_hdmi_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdc2_state_on {
|
||||
cd-pins {
|
||||
pins = "gpio38";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,112 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* IPQ5332 RDP474 board device tree source
|
||||
*
|
||||
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "ipq5332.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9";
|
||||
compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&gpio_keys_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button-wps {
|
||||
label = "wps";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart0 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc {
|
||||
bus-width = <4>;
|
||||
max-frequency = <192000000>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
pinctrl-0 = <&sdc_default_state>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&xo_board {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
/* PINCTRL */
|
||||
|
||||
&tlmm {
|
||||
gpio_keys_default_state: gpio-keys-default-state {
|
||||
pins = "gpio35";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
i2c_1_pins: i2c-1-state {
|
||||
pins = "gpio29", "gpio30";
|
||||
function = "blsp1_i2c0";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
sdc_default_state: sdc-default-state {
|
||||
clk-pins {
|
||||
pins = "gpio13";
|
||||
function = "sdc_clk";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "gpio12";
|
||||
function = "sdc_cmd";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "sdc_data";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -114,6 +114,16 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bootloader@4a100000 {
|
||||
reg = <0x0 0x4a100000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
sbl@4a500000 {
|
||||
reg = <0x0 0x4a500000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tz_mem: tz@4a600000 {
|
||||
reg = <0x0 0x4a600000 0x0 0x200000>;
|
||||
no-map;
|
||||
|
|
@ -121,7 +131,7 @@
|
|||
|
||||
smem@4a800000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x4a800000 0x0 0x00100000>;
|
||||
reg = <0x0 0x4a800000 0x0 0x100000>;
|
||||
no-map;
|
||||
|
||||
hwlocks = <&tcsr_mutex 0>;
|
||||
|
|
@ -225,6 +235,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart1: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078b0000 0x200>;
|
||||
interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
dmas = <&blsp_dma 2>, <&blsp_dma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi0: spi@78b5000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
reg = <0x078b5000 0x600>;
|
||||
|
|
|
|||
|
|
@ -932,6 +932,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 4>;
|
||||
|
||||
trips {
|
||||
nss-top-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nss0-thermal {
|
||||
|
|
@ -939,6 +947,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 5>;
|
||||
|
||||
trips {
|
||||
nss-0-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nss1-thermal {
|
||||
|
|
@ -946,6 +962,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 6>;
|
||||
|
||||
trips {
|
||||
nss-1-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcss-phya0-thermal {
|
||||
|
|
@ -953,6 +977,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 7>;
|
||||
|
||||
trips {
|
||||
wcss-phya0-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcss-phya1-thermal {
|
||||
|
|
@ -960,6 +992,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 8>;
|
||||
|
||||
trips {
|
||||
wcss-phya1-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
|
|
@ -967,6 +1007,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 9>;
|
||||
|
||||
trips {
|
||||
cpu0-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu1_thermal: cpu1-thermal {
|
||||
|
|
@ -974,6 +1022,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 10>;
|
||||
|
||||
trips {
|
||||
cpu1-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu2_thermal: cpu2-thermal {
|
||||
|
|
@ -981,6 +1037,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 11>;
|
||||
|
||||
trips {
|
||||
cpu2-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu3_thermal: cpu3-thermal {
|
||||
|
|
@ -988,6 +1052,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 12>;
|
||||
|
||||
trips {
|
||||
cpu3-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster_thermal: cluster-thermal {
|
||||
|
|
@ -995,6 +1067,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 13>;
|
||||
|
||||
trips {
|
||||
cluster-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcss-phyb0-thermal {
|
||||
|
|
@ -1002,6 +1082,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 14>;
|
||||
|
||||
trips {
|
||||
wcss-phyb0-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcss-phyb1-thermal {
|
||||
|
|
@ -1009,6 +1097,14 @@
|
|||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&tsens 15>;
|
||||
|
||||
trips {
|
||||
wcss-phyb1-crit {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* IPQ9574 RDP454 board device tree source
|
||||
*
|
||||
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ipq9574.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
|
||||
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_spi0 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
regulators {
|
||||
compatible = "qcom,rpm-mp5496-regulators";
|
||||
|
||||
ipq9574_s1: s1 {
|
||||
/*
|
||||
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
|
||||
* During regulator registration, kernel not knowing the initial voltage,
|
||||
* considers it as zero and brings up the regulators with minimum supported voltage.
|
||||
* Update the regulator-min-microvolt with SVS voltage of 725mV so that
|
||||
* the regulators are brought up with 725mV which is sufficient for all the
|
||||
* corner parts to operate at 800MHz
|
||||
*/
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1075000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
spi_0_pins: spi-0-state {
|
||||
pins = "gpio11", "gpio12", "gpio13", "gpio14";
|
||||
function = "blsp0_spi";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&xo_board_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
|
@ -155,6 +155,16 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bootloader@4a100000 {
|
||||
reg = <0x0 0x4a100000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
sbl@4a500000 {
|
||||
reg = <0x0 0x4a500000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tz_region: tz@4a600000 {
|
||||
reg = <0x0 0x4a600000 0x0 0x400000>;
|
||||
no-map;
|
||||
|
|
@ -162,7 +172,7 @@
|
|||
|
||||
smem@4aa00000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x4aa00000 0x0 0x00100000>;
|
||||
reg = <0x0 0x4aa00000 0x0 0x100000>;
|
||||
hwlocks = <&tcsr_mutex 0>;
|
||||
no-map;
|
||||
};
|
||||
|
|
@ -205,6 +215,36 @@
|
|||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
cryptobam: dma-controller@704000 {
|
||||
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
||||
reg = <0x00704000 0x20000>;
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <1>;
|
||||
qcom,controlled-remotely;
|
||||
};
|
||||
|
||||
crypto: crypto@73a000 {
|
||||
compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
|
||||
reg = <0x0073a000 0x6000>;
|
||||
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
|
||||
<&gcc GCC_CRYPTO_AXI_CLK>,
|
||||
<&gcc GCC_CRYPTO_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 2>, <&cryptobam 3>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
tsens: thermal-sensor@4a9000 {
|
||||
compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
|
||||
reg = <0x004a9000 0x1000>,
|
||||
<0x004a8000 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "combined";
|
||||
#qcom,sensors = <16>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq9574-tlmm";
|
||||
reg = <0x01000000 0x300000>;
|
||||
|
|
@ -581,6 +621,214 @@
|
|||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
nss-top-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 3>;
|
||||
|
||||
trips {
|
||||
nss-top-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ubi-0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 4>;
|
||||
|
||||
trips {
|
||||
ubi_0-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ubi-1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 5>;
|
||||
|
||||
trips {
|
||||
ubi_1-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ubi-2-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 6>;
|
||||
|
||||
trips {
|
||||
ubi_2-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ubi-3-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 7>;
|
||||
|
||||
trips {
|
||||
ubi_3-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 8>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 9>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 10>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <120000>;
|
||||
hysteresis = <10000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 11>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <120000>;
|
||||
hysteresis = <10000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu2-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 12>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <120000>;
|
||||
hysteresis = <10000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu3-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 13>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <120000>;
|
||||
hysteresis = <10000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu-passive {
|
||||
temperature = <110000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wcss-phyb-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 14>;
|
||||
|
||||
trips {
|
||||
wcss_phyb-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
top-glue-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&tsens 15>;
|
||||
|
||||
trips {
|
||||
top_glue-critical {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
|
|
|
|||
|
|
@ -133,17 +133,13 @@
|
|||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
|
|
@ -184,6 +180,13 @@
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen-default-state {
|
||||
reset-pins {
|
||||
pins = "gpio12";
|
||||
|
|
|
|||
|
|
@ -171,18 +171,14 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -276,6 +272,13 @@
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ts_int_reset_default: ts-int-reset-default-state {
|
||||
pins = "gpio13", "gpio100";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -139,10 +139,6 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
|
|
@ -150,8 +146,8 @@
|
|||
vmmc-supply = <®_sd_vmmc>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
|
|
@ -205,6 +201,13 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen-default-state {
|
||||
touch-pins {
|
||||
pins = "gpio13";
|
||||
|
|
|
|||
|
|
@ -128,16 +128,12 @@
|
|||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -184,6 +180,13 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen-default-state {
|
||||
reset-pins {
|
||||
pins = "gpio12";
|
||||
|
|
|
|||
|
|
@ -260,18 +260,14 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
/*
|
||||
* The Huawei device tree sets cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>.
|
||||
|
|
@ -299,8 +295,8 @@
|
|||
"AMIC3", "MIC BIAS External1";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cdc_pdm_lines_act>;
|
||||
pinctrl-1 = <&cdc_pdm_lines_sus>;
|
||||
pinctrl-0 = <&cdc_pdm_default>;
|
||||
pinctrl-1 = <&cdc_pdm_sleep>;
|
||||
|
||||
primary-dai-link {
|
||||
link-name = "WCD";
|
||||
|
|
@ -397,7 +393,7 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
sdhc2_cd_default: sdhc2-cd-default-state {
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio56";
|
||||
function = "gpio";
|
||||
|
||||
|
|
|
|||
|
|
@ -242,19 +242,10 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -125,18 +125,14 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -190,6 +186,13 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default-state {
|
||||
pins = "gpio110";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -1,582 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
|
||||
blsp_uart1_default: blsp-uart1-default-state {
|
||||
/* TX, RX, CTS_N, RTS_N */
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "blsp_uart1";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_uart1_sleep: blsp-uart1-sleep-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_uart2_default: blsp-uart2-default-state {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_uart2_sleep: blsp-uart2-sleep-state {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi1_default: blsp-spi1-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio0", "gpio1", "gpio3";
|
||||
function = "blsp_spi1";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi1_sleep: blsp-spi1-sleep-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi2_default: blsp-spi2-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio4", "gpio5", "gpio7";
|
||||
function = "blsp_spi2";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio6";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi2_sleep: blsp-spi2-sleep-state {
|
||||
pins = "gpio4", "gpio5", "gpio6", "gpio7";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi3_default: blsp-spi3-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio8", "gpio9", "gpio11";
|
||||
function = "blsp_spi3";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio10";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi3_sleep: blsp-spi3-sleep-state {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi4_default: blsp-spi4-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio12", "gpio13", "gpio15";
|
||||
function = "blsp_spi4";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio14";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi4_sleep: blsp-spi4-sleep-state {
|
||||
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi5_default: blsp-spi5-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio16", "gpio17", "gpio19";
|
||||
function = "blsp_spi5";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi5_sleep: blsp-spi5-sleep-state {
|
||||
pins = "gpio16", "gpio17", "gpio18", "gpio19";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi6_default: blsp-spi6-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio20", "gpio21", "gpio23";
|
||||
function = "blsp_spi6";
|
||||
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio22";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi6_sleep: blsp-spi6-sleep-state {
|
||||
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_i2c1_default: blsp-i2c1-default-state {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "blsp_i2c1";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c1_sleep: blsp-i2c1-sleep-state {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c2_default: blsp-i2c2-default-state {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "blsp_i2c2";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c2_sleep: blsp-i2c2-sleep-state {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c3_default: blsp-i2c3-default-state {
|
||||
pins = "gpio10", "gpio11";
|
||||
function = "blsp_i2c3";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c3_sleep: blsp-i2c3-sleep-state {
|
||||
pins = "gpio10", "gpio11";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c4_default: blsp-i2c4-default-state {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "blsp_i2c4";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c4_sleep: blsp-i2c4-sleep-state {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c5_default: blsp-i2c5-default-state {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "blsp_i2c5";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c5_sleep: blsp-i2c5-sleep-state {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c6_default: blsp-i2c6-default-state {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "blsp_i2c6";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c6_sleep: blsp-i2c6-sleep-state {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pmx-sdc1-clk-state {
|
||||
sdc1_clk_on: clk-on-pins {
|
||||
pins = "sdc1_clk";
|
||||
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
sdc1_clk_off: clk-off-pins {
|
||||
pins = "sdc1_clk";
|
||||
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc1-cmd-state {
|
||||
sdc1_cmd_on: cmd-on-pins {
|
||||
pins = "sdc1_cmd";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
sdc1_cmd_off: cmd-off-pins {
|
||||
pins = "sdc1_cmd";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc1-data-state {
|
||||
sdc1_data_on: data-on-pins {
|
||||
pins = "sdc1_data";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
sdc1_data_off: data-off-pins {
|
||||
pins = "sdc1_data";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc2-clk-state {
|
||||
sdc2_clk_on: clk-on-pins {
|
||||
pins = "sdc2_clk";
|
||||
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
sdc2_clk_off: clk-off-pins {
|
||||
pins = "sdc2_clk";
|
||||
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc2-cmd-state {
|
||||
sdc2_cmd_on: cmd-on-pins {
|
||||
pins = "sdc2_cmd";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
sdc2_cmd_off: cmd-off-pins {
|
||||
pins = "sdc2_cmd";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc2-data-state {
|
||||
sdc2_data_on: data-on-pins {
|
||||
pins = "sdc2_data";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
sdc2_data_off: data-off-pins {
|
||||
pins = "sdc2_data";
|
||||
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmx-sdc2-cd-pin-state {
|
||||
sdc2_cd_on: cd-on-pins {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
sdc2_cd_off: cd-off-pins {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cdc-pdm-lines-state {
|
||||
cdc_pdm_lines_act: pdm-lines-on-pins {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
cdc_pdm_lines_sus: pdm-lines-off-pins {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
ext-pri-tlmm-lines-state {
|
||||
ext_pri_tlmm_lines_act: ext-pa-on-pins {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
ext_pri_tlmm_lines_sus: ext-pa-off-pins {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
ext-pri-ws-line-state {
|
||||
ext_pri_ws_act: ext-pa-on-pins {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
ext_pri_ws_sus: ext-pa-off-pins {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
ext-mclk-tlmm-lines-state {
|
||||
ext_mclk_tlmm_lines_act: mclk-lines-on-pins {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
ext_mclk_tlmm_lines_sus: mclk-lines-off-pins {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
/* secondary Mi2S */
|
||||
ext-sec-tlmm-lines-state {
|
||||
ext_sec_tlmm_lines_act: tlmm-lines-on-pins {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
ext_sec_tlmm_lines_sus: tlmm-lines-off-pins {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_dmic_lines_act: cdc-dmic-lines-on-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
|
||||
drive-strength = <8>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
|
||||
drive-strength = <8>;
|
||||
};
|
||||
};
|
||||
cdc_dmic_lines_sus: cdc-dmic-lines-off-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
wcnss_pin_a: wcnss-active-state {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
|
||||
function = "wcss_wlan";
|
||||
|
||||
drive-strength = <6>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
cci0_default: cci0-default-state {
|
||||
pins = "gpio29", "gpio30";
|
||||
function = "cci_i2c";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
camera_front_default: camera-front-default-state {
|
||||
pwdn-pins {
|
||||
pins = "gpio33";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
rst-pins {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
mclk1-pins {
|
||||
pins = "gpio27";
|
||||
function = "cam_mclk1";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
camera_rear_default: camera-rear-default-state {
|
||||
pwdn-pins {
|
||||
pins = "gpio34";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
rst-pins {
|
||||
pins = "gpio35";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
mclk0-pins {
|
||||
pins = "gpio26";
|
||||
function = "cam_mclk0";
|
||||
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -263,18 +263,14 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -391,6 +387,13 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tkey_default: tkey-default-state {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -135,16 +135,12 @@
|
|||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -199,4 +195,11 @@
|
|||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -97,18 +97,14 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
@ -162,4 +158,11 @@
|
|||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -276,19 +276,10 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
|
||||
non-removable;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -101,10 +101,6 @@
|
|||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -173,19 +173,10 @@
|
|||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -996,6 +996,485 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
blsp_i2c1_default: blsp-i2c1-default-state {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "blsp_i2c1";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c1_sleep: blsp-i2c1-sleep-state {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c2_default: blsp-i2c2-default-state {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "blsp_i2c2";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c2_sleep: blsp-i2c2-sleep-state {
|
||||
pins = "gpio6", "gpio7";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c3_default: blsp-i2c3-default-state {
|
||||
pins = "gpio10", "gpio11";
|
||||
function = "blsp_i2c3";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c3_sleep: blsp-i2c3-sleep-state {
|
||||
pins = "gpio10", "gpio11";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c4_default: blsp-i2c4-default-state {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "blsp_i2c4";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c4_sleep: blsp-i2c4-sleep-state {
|
||||
pins = "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c5_default: blsp-i2c5-default-state {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "blsp_i2c5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c5_sleep: blsp-i2c5-sleep-state {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c6_default: blsp-i2c6-default-state {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "blsp_i2c6";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_i2c6_sleep: blsp-i2c6-sleep-state {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_spi1_default: blsp-spi1-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio0", "gpio1", "gpio3";
|
||||
function = "blsp_spi1";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi1_sleep: blsp-spi1-sleep-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi2_default: blsp-spi2-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio4", "gpio5", "gpio7";
|
||||
function = "blsp_spi2";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio6";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi2_sleep: blsp-spi2-sleep-state {
|
||||
pins = "gpio4", "gpio5", "gpio6", "gpio7";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi3_default: blsp-spi3-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio8", "gpio9", "gpio11";
|
||||
function = "blsp_spi3";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio10";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi3_sleep: blsp-spi3-sleep-state {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi4_default: blsp-spi4-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio12", "gpio13", "gpio15";
|
||||
function = "blsp_spi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio14";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi4_sleep: blsp-spi4-sleep-state {
|
||||
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi5_default: blsp-spi5-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio16", "gpio17", "gpio19";
|
||||
function = "blsp_spi5";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi5_sleep: blsp-spi5-sleep-state {
|
||||
pins = "gpio16", "gpio17", "gpio18", "gpio19";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_spi6_default: blsp-spi6-default-state {
|
||||
spi-pins {
|
||||
pins = "gpio20", "gpio21", "gpio23";
|
||||
function = "blsp_spi6";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
cs-pins {
|
||||
pins = "gpio22";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
blsp_spi6_sleep: blsp-spi6-sleep-state {
|
||||
pins = "gpio20", "gpio21", "gpio22", "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_uart1_default: blsp-uart1-default-state {
|
||||
/* TX, RX, CTS_N, RTS_N */
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "blsp_uart1";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_uart1_sleep: blsp-uart1-sleep-state {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
blsp_uart2_default: blsp-uart2-default-state {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "blsp_uart2";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
blsp_uart2_sleep: blsp-uart2-sleep-state {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
camera_front_default: camera-front-default-state {
|
||||
pwdn-pins {
|
||||
pins = "gpio33";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
rst-pins {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
mclk1-pins {
|
||||
pins = "gpio27";
|
||||
function = "cam_mclk1";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
camera_rear_default: camera-rear-default-state {
|
||||
pwdn-pins {
|
||||
pins = "gpio34";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
rst-pins {
|
||||
pins = "gpio35";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
mclk0-pins {
|
||||
pins = "gpio26";
|
||||
function = "cam_mclk0";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cci0_default: cci0-default-state {
|
||||
pins = "gpio29", "gpio30";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cdc_dmic_default: cdc-dmic-default-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_dmic_sleep: cdc-dmic-sleep-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_pdm_default: cdc-pdm-default-state {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cdc_pdm_sleep: cdc-pdm-sleep-state {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pri_mi2s_default: mi2s-pri-default-state {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pri_mi2s_sleep: mi2s-pri-sleep-state {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pri_mi2s_ws_default: mi2s-pri-ws-default-state {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sec_mi2s_default: mi2s-sec-default-state {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sec_mi2s_sleep: mi2s-sec-sleep-state {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc1_default: sdc1-default-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_sleep: sdc1-sleep-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_default: sdc2-default-state {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
cmd-pins {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_sleep: sdc2-sleep-state {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
cmd-pins {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
data-pins {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
wcss_wlan_default: wcss-wlan-default-state {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
|
||||
function = "wcss_wlan";
|
||||
drive-strength = <6>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
gcc: clock-controller@1800000 {
|
||||
|
|
@ -1561,6 +2040,9 @@
|
|||
<&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
pinctrl-0 = <&sdc1_default>;
|
||||
pinctrl-1 = <&sdc1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
mmc-ddr-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
|
@ -1579,6 +2061,9 @@
|
|||
<&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1888,7 +2373,7 @@
|
|||
qcom,smem-state-names = "stop";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wcnss_pin_a>;
|
||||
pinctrl-0 = <&wcss_wlan_default>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -2185,5 +2670,3 @@
|
|||
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "msm8916-pins.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,12 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* msm8939-pm8916.dtsi describes common properties (e.g. regulator connections)
|
||||
* that apply to most devices that make use of the MSM8939 SoC and PM8916 PMIC.
|
||||
* Many regulators have a fixed purpose in the original reference design and
|
||||
* were rarely re-used for different purposes. Devices that deviate from the
|
||||
* typical reference design should not make use of this include and instead add
|
||||
* the necessary properties in the board-specific device tree.
|
||||
*/
|
||||
|
||||
#include "msm8939.dtsi"
|
||||
#include "pm8916.dtsi"
|
||||
|
|
@ -25,33 +33,104 @@
|
|||
pll-supply = <&pm8916_l7>;
|
||||
};
|
||||
|
||||
&pm8916_codec {
|
||||
vdd-cdc-io-supply = <&pm8916_l5>;
|
||||
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
|
||||
vdd-micbias-supply = <&pm8916_l13>;
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
smd_rpm_regulators: regulators {
|
||||
pm8916_rpm_regulators: regulators {
|
||||
compatible = "qcom,rpm-pm8916-regulators";
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
/* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */
|
||||
/* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */
|
||||
pm8916_s3: s3 {};
|
||||
pm8916_s4: s4 {};
|
||||
pm8916_s3: s3 {
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on; /* Needed for L2 */
|
||||
};
|
||||
pm8916_s4: s4 {
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <2150000>;
|
||||
regulator-always-on; /* Needed for L5/L7 */
|
||||
};
|
||||
|
||||
/*
|
||||
* Some of the regulators are unused or managed by another
|
||||
* processor (e.g. the modem). We should still define nodes for
|
||||
* them to ensure the vote from the application processor can be
|
||||
* dropped in case the regulators are already on during boot.
|
||||
*
|
||||
* The labels for these nodes are omitted on purpose because
|
||||
* boards should configure a proper voltage before using them.
|
||||
*/
|
||||
l1 {};
|
||||
|
||||
pm8916_l2: l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on; /* Needed for LPDDR RAM */
|
||||
};
|
||||
|
||||
pm8916_l1: l1 {};
|
||||
pm8916_l2: l2 {};
|
||||
/* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */
|
||||
pm8916_l4: l4 {};
|
||||
pm8916_l5: l5 {};
|
||||
pm8916_l6: l6 {};
|
||||
pm8916_l7: l7 {};
|
||||
pm8916_l8: l8 {};
|
||||
pm8916_l9: l9 {};
|
||||
pm8916_l10: l10 {};
|
||||
pm8916_l11: l11 {};
|
||||
pm8916_l12: l12 {};
|
||||
pm8916_l13: l13 {};
|
||||
pm8916_l14: l14 {};
|
||||
pm8916_l15: l15 {};
|
||||
pm8916_l16: l16 {};
|
||||
pm8916_l17: l17 {};
|
||||
pm8916_l18: l18 {};
|
||||
|
||||
l4 {};
|
||||
|
||||
pm8916_l5: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on; /* Needed for most digital I/O */
|
||||
};
|
||||
|
||||
pm8916_l6: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l7: l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on; /* Needed for CPU PLL */
|
||||
};
|
||||
|
||||
pm8916_l8: l8 {
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
pm8916_l9: l9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l10 {};
|
||||
|
||||
pm8916_l11: l11 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-system-load = <200000>;
|
||||
};
|
||||
|
||||
pm8916_l12: l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
pm8916_l13: l13 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
|
||||
l14 {};
|
||||
l15 {};
|
||||
l16 {};
|
||||
l17 {};
|
||||
l18 {};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,13 @@
|
|||
};
|
||||
|
||||
&tlmm {
|
||||
sdc2_cd_default: sdc2-cd-default-state {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb_id_default: usb-id-default-state {
|
||||
pins = "gpio110";
|
||||
function = "gpio";
|
||||
|
|
@ -51,115 +58,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
&smd_rpm_regulators {
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
pm8916_s3: s3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
pm8916_s4: s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
};
|
||||
|
||||
pm8916_l2: l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
pm8916_l4: l4 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
};
|
||||
|
||||
pm8916_l5: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l6: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
pm8916_l7: l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8916_l8: l8 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
pm8916_l9: l9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l10: l10 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l11: l11 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-system-load = <200000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
pm8916_l12: l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l13: l13 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
|
||||
pm8916_l14: l14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l15: l15 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l16: l16 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
pm8916_l17: l17 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
pm8916_l18: l18 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
pinctrl-0 = <&sdc1_default_state>;
|
||||
pinctrl-1 = <&sdc1_sleep_state>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
pinctrl-0 = <&sdc2_default_state>;
|
||||
pinctrl-1 = <&sdc2_sleep_state>;
|
||||
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
|
||||
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -969,7 +969,37 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
cdc_pdm_lines_default: pdm-lines-default-state {
|
||||
cdc_dmic_default: cdc-dmic-default-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_dmic_sleep: cdc-dmic-sleep-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
cdc_pdm_default: cdc-pdm-default-state {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
|
|
@ -977,7 +1007,7 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
cdc_pdm_lines_sleep: pdm-lines-suspend-state {
|
||||
cdc_pdm_sleep: cdc-pdm-sleep-state {
|
||||
pins = "gpio63", "gpio64", "gpio65", "gpio66",
|
||||
"gpio67", "gpio68";
|
||||
function = "cdc_pdm0";
|
||||
|
|
@ -985,102 +1015,63 @@
|
|||
bias-pull-down;
|
||||
};
|
||||
|
||||
cdc_dmic_lines_act: cdc-dmic-lines-on-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
pri_mi2s_default: mi2s-pri-default-state {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cdc_dmic_lines_sus: cdc-dmic-lines-off-state {
|
||||
clk-pins {
|
||||
pins = "gpio0";
|
||||
function = "dmic0_clk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "gpio1";
|
||||
function = "dmic0_data";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
pri_mi2s_sleep: mi2s-pri-sleep-state {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext-mclk-tlmm-lines-state {
|
||||
ext_mclk_tlmm_lines_act: mclk-lines-on-pins {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext_mclk_tlmm_lines_sus: mclk-lines-off-pins {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext-pri-tlmm-lines-state {
|
||||
ext_pri_tlmm_lines_act: ext-pa-on-pins {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext_pri_tlmm_lines_sus: ext-pa-off-pins {
|
||||
pins = "gpio113", "gpio114", "gpio115", "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
|
||||
pins = "gpio116";
|
||||
function = "pri_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext-pri-ws-line-state {
|
||||
ext_pri_ws_act: ext-pa-on-pins {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext_pri_ws_sus: ext-pa-off-pins {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
pri_mi2s_ws_default: mi2s-pri-ws-default-state {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
/* secondary Mi2S */
|
||||
ext-sec-tlmm-lines-state {
|
||||
ext_sec_tlmm_lines_act: tlmm-lines-on-pins {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ext_sec_tlmm_lines_sus: tlmm-lines-off-pins {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
|
||||
pins = "gpio110";
|
||||
function = "pri_mi2s_ws";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc1_default_state: sdc1-default-state {
|
||||
sec_mi2s_default: mi2s-sec-default-state {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sec_mi2s_sleep: mi2s-sec-sleep-state {
|
||||
pins = "gpio112", "gpio117", "gpio118", "gpio119";
|
||||
function = "sec_mi2s";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc1_default: sdc1-default-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
|
|
@ -1100,7 +1091,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdc1_sleep_state: sdc1-sleep-state {
|
||||
sdc1_sleep: sdc1-sleep-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
bias-disable;
|
||||
|
|
@ -1120,7 +1111,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdc2_default_state: sdc2-default-state {
|
||||
sdc2_default: sdc2-default-state {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
|
|
@ -1138,16 +1129,9 @@
|
|||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
cd-pins {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_sleep_state: sdc2-sleep-state {
|
||||
sdc2_sleep: sdc2-sleep-state {
|
||||
clk-pins {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
|
|
@ -1165,16 +1149,9 @@
|
|||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
cd-pins {
|
||||
pins = "gpio38";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
wcnss_pin_a: wcnss-active-state {
|
||||
wcss_wlan_default: wcss-wlan-default-state {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
|
||||
function = "wcss_wlan";
|
||||
drive-strength = <6>;
|
||||
|
|
@ -1631,6 +1608,7 @@
|
|||
<&gcc GCC_CODEC_DIGCODEC_CLK>;
|
||||
clock-names = "ahbix-clk", "mclk";
|
||||
#sound-dai-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhc_1: mmc@7824900 {
|
||||
|
|
@ -1646,6 +1624,9 @@
|
|||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
resets = <&gcc GCC_SDCC1_BCR>;
|
||||
pinctrl-0 = <&sdc1_default>;
|
||||
pinctrl-1 = <&sdc1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
mmc-ddr-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
|
@ -1665,6 +1646,9 @@
|
|||
<&rpmcc RPM_SMD_XO_CLK_SRC>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1980,7 +1964,7 @@
|
|||
qcom,smem-state-names = "stop";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wcnss_pin_a>;
|
||||
pinctrl-0 = <&wcss_wlan_default>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
|
|||
|
|
@ -764,10 +764,10 @@
|
|||
#power-domain-cells = <1>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dsi1_phy 0>;
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&mdss_dsi1_phy 0>;
|
||||
clock-names = "xo",
|
||||
"sleep",
|
||||
"dsi0pll",
|
||||
|
|
@ -849,20 +849,20 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp5_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@1a94000 {
|
||||
mdss_dsi0: dsi@1a94000 {
|
||||
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x01a94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
|
@ -872,8 +872,8 @@
|
|||
|
||||
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
|
||||
<&gcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_AHB_CLK>,
|
||||
|
|
@ -888,7 +888,7 @@
|
|||
"pixel",
|
||||
"core";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -901,20 +901,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@1a94400 {
|
||||
mdss_dsi0_phy: phy@1a94400 {
|
||||
compatible = "qcom,dsi-phy-14nm-8953";
|
||||
reg = <0x01a94400 0x100>,
|
||||
<0x01a94500 0x300>,
|
||||
|
|
@ -932,7 +932,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi1: dsi@1a96000 {
|
||||
mdss_dsi1: dsi@1a96000 {
|
||||
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x01a96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
|
@ -942,8 +942,8 @@
|
|||
|
||||
assigned-clocks = <&gcc BYTE1_CLK_SRC>,
|
||||
<&gcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_AHB_CLK>,
|
||||
|
|
@ -958,7 +958,7 @@
|
|||
"pixel",
|
||||
"core";
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -968,20 +968,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@1a96400 {
|
||||
mdss_dsi1_phy: phy@1a96400 {
|
||||
compatible = "qcom,dsi-phy-14nm-8953";
|
||||
reg = <0x01a96400 0x100>,
|
||||
<0x01a96500 0x300>,
|
||||
|
|
|
|||
|
|
@ -24,10 +24,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
&mdss_hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_phy {
|
||||
&mdss_hdmi_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -164,21 +164,6 @@
|
|||
vdda-supply = <&vreg_l2a_1p25>;
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
vdda-supply = <&vreg_l2a_1p25>;
|
||||
vcca-supply = <&vreg_l22a_3p0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
vcca-supply = <&vreg_l28a_0p925>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb_phy1 {
|
||||
vdd-supply = <&vreg_l28a_0p925>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
|
|
@ -201,6 +186,21 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vreg_l2a_1p25>;
|
||||
vcca-supply = <&vreg_l22a_3p0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vcca-supply = <&vreg_l28a_0p925>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmcc {
|
||||
vdd-gfx-supply = <&vdd_gfx>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -235,7 +235,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l2a_1p25>;
|
||||
|
|
@ -246,26 +254,18 @@
|
|||
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
&mdss_dsi0_out {
|
||||
status = "okay";
|
||||
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
|
||||
vcca-supply = <&vreg_l28a_0p925>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmcc {
|
||||
vdd-gfx-supply = <&vdd_gfx>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -93,7 +93,13 @@
|
|||
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
&gpu {
|
||||
zap-shader {
|
||||
firmware-name = "qcom/msm8996/gemini/a530_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l2a_1p25>;
|
||||
|
|
@ -112,22 +118,16 @@
|
|||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
zap-shader {
|
||||
firmware-name = "qcom/msm8996/gemini/a530_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&pmi8994_wled {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -889,11 +889,11 @@
|
|||
clocks = <&xo_board>,
|
||||
<&gcc GPLL0>,
|
||||
<&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&hdmi_phy>;
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_hdmi_phy>;
|
||||
clock-names = "xo",
|
||||
"gpll0",
|
||||
"gcc_mmss_noc_cfg_ahb_clk",
|
||||
|
|
@ -978,27 +978,27 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf3_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
remote-endpoint = <&mdss_hdmi_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
mdp5_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@994000 {
|
||||
mdss_dsi0: dsi@994000 {
|
||||
compatible = "qcom,msm8996-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x00994000 0x400>;
|
||||
|
|
@ -1022,9 +1022,9 @@
|
|||
"pixel",
|
||||
"core";
|
||||
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1036,20 +1036,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@994400 {
|
||||
mdss_dsi0_phy: phy@994400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x00994400 0x100>,
|
||||
<0x00994500 0x300>,
|
||||
|
|
@ -1066,7 +1066,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi1: dsi@996000 {
|
||||
mdss_dsi1: dsi@996000 {
|
||||
compatible = "qcom,msm8996-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x00996000 0x400>;
|
||||
|
|
@ -1090,9 +1090,9 @@
|
|||
"pixel",
|
||||
"core";
|
||||
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1104,20 +1104,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@996400 {
|
||||
mdss_dsi1_phy: phy@996400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x00996400 0x100>,
|
||||
<0x00996500 0x300>,
|
||||
|
|
@ -1134,8 +1134,8 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi: hdmi-tx@9a0000 {
|
||||
compatible = "qcom,hdmi-tx-8996";
|
||||
mdss_hdmi: mdss_hdmi-tx@9a0000 {
|
||||
compatible = "qcom,mdss_hdmi-tx-8996";
|
||||
reg = <0x009a0000 0x50c>,
|
||||
<0x00070000 0x6158>,
|
||||
<0x009e0000 0xfff>;
|
||||
|
|
@ -1158,7 +1158,7 @@
|
|||
"alt_iface",
|
||||
"extp";
|
||||
|
||||
phys = <&hdmi_phy>;
|
||||
phys = <&mdss_hdmi_phy>;
|
||||
#sound-dai-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -1169,16 +1169,16 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
mdss_hdmi_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf3_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_phy: phy@9a0600 {
|
||||
mdss_hdmi_phy: phy@9a0600 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "qcom,hdmi-phy-8996";
|
||||
compatible = "qcom,mdss_hdmi-phy-8996";
|
||||
reg = <0x009a0600 0x1c4>,
|
||||
<0x009a0a00 0x124>,
|
||||
<0x009a0c00 0x124>,
|
||||
|
|
|
|||
|
|
@ -39,7 +39,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
&gpu {
|
||||
zap-shader {
|
||||
firmware-name = "qcom/msm8996/natrium/a530_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
|
||||
vdda-supply = <&vreg_l2a_1p25>;
|
||||
|
|
@ -57,22 +63,16 @@
|
|||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
zap-shader {
|
||||
firmware-name = "qcom/msm8996/natrium/a530_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/msm8996/natrium/mba.mbn",
|
||||
"qcom/msm8996/natrium/modem.mbn";
|
||||
|
|
|
|||
|
|
@ -24,101 +24,121 @@
|
|||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <307200>;
|
||||
};
|
||||
opp-768000000 {
|
||||
opp-hz = /bits/ 64 <768000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <307200>;
|
||||
};
|
||||
opp-844800000 {
|
||||
opp-hz = /bits/ 64 <844800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <384000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <441600>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <537600>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <614400>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <691200>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <768000>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <844800>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <902400>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <979200>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1132800>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1190400>;
|
||||
};
|
||||
opp-1996800000 {
|
||||
opp-hz = /bits/ 64 <1996800000>;
|
||||
opp-supported-hw = <0x20>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1516800>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1593600>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -131,136 +151,163 @@
|
|||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <192000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <307200>;
|
||||
};
|
||||
opp-748800000 {
|
||||
opp-hz = /bits/ 64 <748800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <307200>;
|
||||
};
|
||||
opp-825600000 {
|
||||
opp-hz = /bits/ 64 <825600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <384000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <441600>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <441600>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <537600>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <614400>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <691200>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <768000>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <844800>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <902400>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <979200>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1056000>;
|
||||
};
|
||||
opp-1670400000 {
|
||||
opp-hz = /bits/ 64 <1670400000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1132800>;
|
||||
};
|
||||
opp-1747200000 {
|
||||
opp-hz = /bits/ 64 <1747200000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1190400>;
|
||||
};
|
||||
opp-1824000000 {
|
||||
opp-hz = /bits/ 64 <1824000000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1286400>;
|
||||
};
|
||||
opp-1900800000 {
|
||||
opp-hz = /bits/ 64 <1900800000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1363200>;
|
||||
};
|
||||
opp-1977600000 {
|
||||
opp-hz = /bits/ 64 <1977600000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1440000>;
|
||||
};
|
||||
opp-2054400000 {
|
||||
opp-hz = /bits/ 64 <2054400000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1516800>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1593600>;
|
||||
};
|
||||
opp-2246400000 {
|
||||
opp-hz = /bits/ 64 <2246400000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1593600>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
opp-peak-kBps = <1593600>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -289,3 +336,7 @@
|
|||
};
|
||||
/* The rest is inherited from msm8996 */
|
||||
};
|
||||
|
||||
&cbf {
|
||||
compatible = "qcom,msm8996pro-cbf";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -279,10 +279,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8998_rradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -61,5 +61,15 @@
|
|||
reg = <0xee00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pm8550_pwm: pwm {
|
||||
compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,26 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmi8998_charger: charger@1000 {
|
||||
compatible = "qcom,pmi8998-charger";
|
||||
reg = <0x1000>;
|
||||
|
||||
interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
|
||||
<0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
|
||||
<0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
|
||||
<0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "usb-plugin",
|
||||
"bat-ov",
|
||||
"wdog-bark",
|
||||
"usbin-icl-change";
|
||||
|
||||
io-channels = <&pmi8998_rradc 3>,
|
||||
<&pmi8998_rradc 4>;
|
||||
io-channel-names = "usbin_i", "usbin_v";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmi8998_gpios: gpio@c000 {
|
||||
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
|
|
@ -23,8 +43,6 @@
|
|||
compatible = "qcom,pmi8998-rradc";
|
||||
reg = <0x4500>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@
|
|||
reg = <0x6100>, <0x6200>;
|
||||
reg-names = "rtc", "alarm";
|
||||
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmk8550_sdam_2: nvram@7100 {
|
||||
|
|
|
|||
|
|
@ -48,6 +48,8 @@
|
|||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
|
|
@ -64,6 +66,8 @@
|
|||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
|
|
@ -76,6 +80,8 @@
|
|||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
|
|
@ -88,6 +94,8 @@
|
|||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
|
|
@ -109,6 +117,30 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41000043>;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <2118>;
|
||||
min-residency-us = <7376>;
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "power-collapse";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
entry-latency-us = <290>;
|
||||
exit-latency-us = <376>;
|
||||
min-residency-us = <1182>;
|
||||
local-timer-stop;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
|
@ -134,6 +166,35 @@
|
|||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cpu-cluster {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
|
|||
|
|
@ -448,6 +448,29 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc {
|
||||
pinctrl-0 = <&sdc_on_state>;
|
||||
pinctrl-1 = <&sdc_off_state>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
cap-mmc-hw-reset;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
|
||||
supports-cqe;
|
||||
|
||||
vmmc-supply = <&vreg_l10a_2p95>;
|
||||
vqmmc-supply = <&vreg_l7a_1p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -842,6 +842,53 @@
|
|||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
sdhc: mmc@8804000 {
|
||||
compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0x0 0x08804000 0x0 0x1000>,
|
||||
<0x0 0x08805000 0x0 0x1000>;
|
||||
reg-names = "hc", "cqhci";
|
||||
|
||||
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC5_AHB_CLK>,
|
||||
<&gcc GCC_SDCC5_APPS_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface",
|
||||
"core",
|
||||
"xo";
|
||||
|
||||
resets = <&gcc GCC_SDCC5_BCR>;
|
||||
|
||||
interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
|
||||
interconnect-names = "sdhc-ddr", "cpu-sdhc";
|
||||
power-domains = <&rpmhpd QDU1000_CX>;
|
||||
operating-points-v2 = <&sdhc1_opp_table>;
|
||||
|
||||
iommus = <&apps_smmu 0x80 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
bus-width = <8>;
|
||||
|
||||
qcom,dll-config = <0x0007642c>;
|
||||
qcom,ddr-config = <0x80040868>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
sdhc1_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
opp-peak-kBps = <6528000 1652800>;
|
||||
opp-avg-kBps = <400000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
|
||||
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
|
||||
|
|
@ -1100,6 +1147,69 @@
|
|||
pins = "gpio31";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
sdc_on_state: sdc-on-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rclk-pins {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sdc_off_state: sdc-off-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rclk-pins {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sram@14680000 {
|
||||
compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
|
||||
reg = <0 0x14680000 0 0x1000>;
|
||||
ranges = <0 0 0x14680000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pil-reloc@94c {
|
||||
compatible = "qcom,pil-reloc-info";
|
||||
reg = <0x94c 0xc8>;
|
||||
};
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
|
|
@ -1242,6 +1352,7 @@
|
|||
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>, <CONTROL_TCS 0>;
|
||||
label = "apps_rsc";
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "sm4250.dtsi"
|
||||
#include "pm6125.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. QRB4210 RB2";
|
||||
|
|
@ -28,6 +29,23 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
label = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&kypd_vol_up_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-volume-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
|
@ -219,6 +237,25 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pm6125_gpios {
|
||||
kypd_vol_up_n: kypd-vol-up-n-state {
|
||||
pins = "gpio5";
|
||||
function = "normal";
|
||||
power-source = <0>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -535,30 +535,6 @@
|
|||
firmware-name = "qcom/sm8250/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
|
||||
#if 0
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
#endif
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
};
|
||||
|
||||
&gmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -604,7 +580,7 @@
|
|||
reg = <0>;
|
||||
|
||||
lt9611_a: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -613,7 +589,7 @@
|
|||
reg = <1>;
|
||||
|
||||
lt9611_b: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
remote-endpoint = <&mdss_dsi1_out>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -639,8 +615,28 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
|
||||
#if 0
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
#endif
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
};
|
||||
|
||||
&pm8150_adc {
|
||||
|
|
|
|||
|
|
@ -171,6 +171,7 @@
|
|||
|
||||
/* Marvell 88EA1512 */
|
||||
rgmii_phy: phy@8 {
|
||||
compatible = "ethernet-phy-id0141.0dd4";
|
||||
reg = <0x8>;
|
||||
|
||||
interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
|
|
|||
|
|
@ -167,6 +167,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gpucc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu_smmu {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie2a {
|
||||
compatible = "qcom,pcie-sa8540p";
|
||||
|
||||
|
|
|
|||
|
|
@ -143,21 +143,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
vdda-supply = <&vreg_l3c_1p2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
vdds-supply = <&vreg_l4a_0p8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
|
@ -269,7 +254,7 @@
|
|||
reg = <0>;
|
||||
|
||||
sn65dsi86_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -313,6 +298,21 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vreg_l3c_1p2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vdds-supply = <&vreg_l4a_0p8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm6150_adc {
|
||||
thermistor@4e {
|
||||
reg = <ADC5_AMUX_THM2_100K_PU>;
|
||||
|
|
|
|||
|
|
@ -295,7 +295,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
|
||||
vdda-supply = <&vreg_l3c_1p2>;
|
||||
|
|
@ -314,7 +318,7 @@
|
|||
|
||||
port {
|
||||
panel0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -329,15 +333,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l4a_0p8>;
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qfprom {
|
||||
vcc-supply = <&vreg_l11a_1p8>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,10 +46,6 @@
|
|||
|
||||
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&ps8640_in>;
|
||||
};
|
||||
|
||||
edp_brij_i2c: &i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -74,7 +70,7 @@ edp_brij_i2c: &i2c2 {
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
ps8640_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -102,6 +98,10 @@ edp_brij_i2c: &i2c2 {
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&ps8640_in>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
edp_brij_ps8640_rst: edp-brij-ps8640-rst-state {
|
||||
pins = "gpio11";
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
compatible = "google,quackingstick-sku1537", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
&mdss_dsi0_phy {
|
||||
qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
|
||||
qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>;
|
||||
qcom,phy-drive-ldo-level = <375>;
|
||||
|
|
|
|||
|
|
@ -52,36 +52,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
panel: panel@0 {
|
||||
/* Compatible will be filled in per-board */
|
||||
reg = <0>;
|
||||
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_rst>;
|
||||
avdd-supply = <&ppvar_lcd>;
|
||||
pp1800-supply = <&v1p8_disp>;
|
||||
pp3300-supply = <&pp3300_dx_edp>;
|
||||
backlight = <&backlight>;
|
||||
rotation = <270>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_keys {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -106,6 +76,36 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
panel: panel@0 {
|
||||
/* Compatible will be filled in per-board */
|
||||
reg = <0>;
|
||||
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_rst>;
|
||||
avdd-supply = <&ppvar_lcd>;
|
||||
pp1800-supply = <&v1p8_disp>;
|
||||
pp3300-supply = <&pp3300_dx_edp>;
|
||||
backlight = <&backlight>;
|
||||
rotation = <270>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,10 +27,6 @@
|
|||
|
||||
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
};
|
||||
|
||||
edp_brij_i2c: &i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -65,7 +61,7 @@ edp_brij_i2c: &i2c2 {
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
sn65dsi86_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -95,6 +91,10 @@ edp_brij_i2c: &i2c2 {
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
edp_brij_irq: edp-brij-irq-state {
|
||||
pins = "gpio11";
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
compatible = "google,wormdingler-sku1024", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
&mdss_dsi0_phy {
|
||||
qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>;
|
||||
qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>;
|
||||
qcom,phy-drive-ldo-level = <450>;
|
||||
|
|
|
|||
|
|
@ -110,37 +110,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
|
||||
panel: panel@0 {
|
||||
reg = <0>;
|
||||
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_reset_1800>;
|
||||
avdd-supply = <&avdd_lcd>;
|
||||
avee-supply = <&avee_lcd>;
|
||||
pp1800-supply = <&v1p8_mipi>;
|
||||
pp3300-supply = <&pp3300_dx_edp>;
|
||||
backlight = <&backlight>;
|
||||
rotation = <270>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -162,6 +131,37 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
|
||||
panel: panel@0 {
|
||||
reg = <0>;
|
||||
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_reset_1800>;
|
||||
avdd-supply = <&avdd_lcd>;
|
||||
avee-supply = <&avee_lcd>;
|
||||
pp1800-supply = <&v1p8_mipi>;
|
||||
pp3300-supply = <&pp3300_dx_edp>;
|
||||
backlight = <&backlight>;
|
||||
rotation = <270>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm6150_adc {
|
||||
skin-temp-thermistor@4d {
|
||||
reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
|
|
|
|||
|
|
@ -705,20 +705,6 @@ ap_h1_spi: &spi0 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
ap_sar_sensor_i2c: &i2c5 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -836,6 +822,20 @@ hp_i2c: &i2c9 {
|
|||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&pm6150_adc {
|
||||
charger-thermistor@4f {
|
||||
reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
|
|
|
|||
|
|
@ -2996,7 +2996,7 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -3033,7 +3033,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@ae94000 {
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sc7180-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae94000 0 0x400>;
|
||||
|
|
@ -3056,12 +3056,12 @@
|
|||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
|
||||
phys = <&dsi_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3074,14 +3074,14 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3106,13 +3106,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi_phy: phy@ae94400 {
|
||||
mdss_dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0 0x0ae94400 0 0x200>,
|
||||
<0 0x0ae94600 0 0x280>,
|
||||
<0 0x0ae94a00 0 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
reg-names = "dsi0_phy",
|
||||
"dsi0_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
|
@ -3203,8 +3203,8 @@
|
|||
reg = <0 0x0af00000 0 0x200000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
|
|
|
|||
|
|
@ -467,10 +467,6 @@ ap_i2c_tpm: &i2c14 {
|
|||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* NVMe drive, enabled on a per-board basis */
|
||||
&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -3872,8 +3872,6 @@
|
|||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3881,7 +3879,7 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -3966,14 +3964,14 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -291,10 +291,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dispcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -2310,7 +2310,8 @@
|
|||
};
|
||||
|
||||
adreno_smmu: iommu@2ca0000 {
|
||||
compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
|
||||
compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
|
||||
"qcom,smmu-500", "arm,mmu-500";
|
||||
reg = <0 0x02ca0000 0 0x10000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <1>;
|
||||
|
|
@ -2732,14 +2733,14 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2783,7 +2784,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@ae94000 {
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae94000 0 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
|
@ -2807,7 +2808,7 @@
|
|||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC8180X_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -2818,14 +2819,14 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -2850,7 +2851,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0_phy: dsi-phy@ae94400 {
|
||||
mdss_dsi0_phy: dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0 0x0ae94400 0 0x200>,
|
||||
<0 0x0ae94600 0 0x280>,
|
||||
|
|
@ -2869,7 +2870,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi1: dsi@ae96000 {
|
||||
mdss_dsi1: dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae96000 0 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
|
@ -2893,7 +2894,7 @@
|
|||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SC8180X_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -2904,20 +2905,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: dsi-phy@ae96400 {
|
||||
mdss_dsi1_phy: dsi-phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0 0x0ae96400 0 0x200>,
|
||||
<0 0x0ae96600 0 0x280>,
|
||||
|
|
@ -2965,7 +2966,7 @@
|
|||
#sound-dai-cells = <0>;
|
||||
|
||||
operating-points-v2 = <&dp0_opp_table>;
|
||||
power-domains = <&rpmhpd SC8180X_CX>;
|
||||
power-domains = <&rpmhpd SC8180X_MMCX>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -3039,7 +3040,7 @@
|
|||
#sound-dai-cells = <0>;
|
||||
|
||||
operating-points-v2 = <&dp0_opp_table>;
|
||||
power-domains = <&rpmhpd SC8180X_CX>;
|
||||
power-domains = <&rpmhpd SC8180X_MMCX>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -3113,7 +3114,7 @@
|
|||
#sound-dai-cells = <0>;
|
||||
|
||||
operating-points-v2 = <&edp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8180X_CX>;
|
||||
power-domains = <&rpmhpd SC8180X_MMCX>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -3495,6 +3496,7 @@
|
|||
<WAKE_TCS 1>,
|
||||
<CONTROL_TCS 0>;
|
||||
label = "apps_rsc";
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -210,6 +210,11 @@
|
|||
};
|
||||
|
||||
reserved-memory {
|
||||
gpu_mem: gpu-mem@8bf00000 {
|
||||
reg = <0 0x8bf00000 0 0x2000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x8000000>;
|
||||
|
|
@ -390,6 +395,15 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mdss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -264,6 +264,11 @@
|
|||
};
|
||||
|
||||
reserved-memory {
|
||||
gpu_mem: gpu-mem@8bf00000 {
|
||||
reg = <0 0x8bf00000 0 0x2000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x8000000>;
|
||||
|
|
@ -518,6 +523,15 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_mem>;
|
||||
firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&mdss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,7 +6,9 @@
|
|||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
|
||||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
|
@ -2331,6 +2333,180 @@
|
|||
reg = <0x0 0x01fc0000 0x0 0x30000>;
|
||||
};
|
||||
|
||||
gpu: gpu@3d00000 {
|
||||
compatible = "qcom,adreno-690.0", "qcom,adreno";
|
||||
|
||||
reg = <0 0x03d00000 0 0x40000>,
|
||||
<0 0x03d9e000 0 0x1000>,
|
||||
<0 0x03d61000 0 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_mem",
|
||||
"cx_dbgc";
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
qcom,gmu = <&gmu>;
|
||||
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "gfx-mem";
|
||||
#cooling-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
opp-peak-kBps = <451000>;
|
||||
};
|
||||
|
||||
opp-410000000 {
|
||||
opp-hz = /bits/ 64 <410000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
opp-peak-kBps = <1555000>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
opp-peak-kBps = <1555000>;
|
||||
};
|
||||
|
||||
opp-547000000 {
|
||||
opp-hz = /bits/ 64 <547000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
||||
opp-peak-kBps = <1555000>;
|
||||
};
|
||||
|
||||
opp-606000000 {
|
||||
opp-hz = /bits/ 64 <606000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
opp-peak-kBps = <2736000>;
|
||||
};
|
||||
|
||||
opp-640000000 {
|
||||
opp-hz = /bits/ 64 <640000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
||||
opp-peak-kBps = <2736000>;
|
||||
};
|
||||
|
||||
opp-655000000 {
|
||||
opp-hz = /bits/ 64 <655000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
opp-peak-kBps = <2736000>;
|
||||
};
|
||||
|
||||
opp-690000000 {
|
||||
opp-hz = /bits/ 64 <690000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
opp-peak-kBps = <2736000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmu: gmu@3d6a000 {
|
||||
compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
|
||||
reg = <0 0x03d6a000 0 0x34000>,
|
||||
<0 0x03de0000 0 0x10000>,
|
||||
<0 0x0b290000 0 0x10000>;
|
||||
reg-names = "gmu", "rscc", "gmu_pdc";
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
clock-names = "gmu",
|
||||
"cxo",
|
||||
"axi",
|
||||
"memnoc",
|
||||
"ahb",
|
||||
"hub",
|
||||
"smmu_vote";
|
||||
power-domains = <&gpucc GPU_CC_CX_GDSC>,
|
||||
<&gpucc GPU_CC_GX_GDSC>;
|
||||
power-domain-names = "cx",
|
||||
"gx";
|
||||
iommus = <&gpu_smmu 5 0xc00>;
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
|
||||
gmu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpucc: clock-controller@3d90000 {
|
||||
compatible = "qcom,sc8280xp-gpucc";
|
||||
reg = <0 0x03d90000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
|
||||
power-domains = <&rpmhpd SC8280XP_GFX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gpu_smmu: iommu@3da0000 {
|
||||
compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
|
||||
"qcom,smmu-500", "arm,mmu-500";
|
||||
reg = <0 0x03da0000 0 0x20000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
||||
<&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
||||
<&gpucc GPU_CC_HUB_AON_CLK>;
|
||||
clock-names = "gcc_gpu_memnoc_gfx_clk",
|
||||
"gcc_gpu_snoc_dvm_gfx_clk",
|
||||
"gpu_cc_ahb_clk",
|
||||
"gpu_cc_hlos1_vote_gpu_smmu_clk",
|
||||
"gpu_cc_cx_gmu_clk",
|
||||
"gpu_cc_hub_cx_int_clk",
|
||||
"gpu_cc_hub_aon_clk";
|
||||
|
||||
power-domains = <&gpucc GPU_CC_CX_GDSC>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
usb_0_hsphy: phy@88e5000 {
|
||||
compatible = "qcom,sc8280xp-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-5nm-phy";
|
||||
|
|
@ -2551,6 +2727,8 @@
|
|||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rxmacro>;
|
||||
clock-names = "iface";
|
||||
resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
label = "RX";
|
||||
|
||||
qcom,din-ports = <0>;
|
||||
|
|
@ -2625,6 +2803,8 @@
|
|||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&wsamacro>;
|
||||
clock-names = "iface";
|
||||
resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
label = "WSA";
|
||||
|
||||
qcom,din-ports = <2>;
|
||||
|
|
@ -2647,6 +2827,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lpass_audiocc: clock-controller@32a9000 {
|
||||
compatible = "qcom,sc8280xp-lpassaudiocc";
|
||||
reg = <0 0x032a9000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
swr2: soundwire-controller@3330000 {
|
||||
compatible = "qcom,soundwire-v1.6.0";
|
||||
reg = <0 0x03330000 0 0x2000>;
|
||||
|
|
@ -2656,6 +2843,8 @@
|
|||
|
||||
clocks = <&txmacro>;
|
||||
clock-names = "iface";
|
||||
resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
|
||||
reset-names = "swr_audio_cgcr";
|
||||
label = "TX";
|
||||
#sound-dai-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -2845,6 +3034,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
lpasscc: clock-controller@33e0000 {
|
||||
compatible = "qcom,sc8280xp-lpasscc";
|
||||
reg = <0 0x033e0000 0 0x12000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
sdc2: mmc@8804000 {
|
||||
compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0 0x08804000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@
|
|||
reg = <0>;
|
||||
|
||||
adv7533_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -183,25 +183,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l1a_1p225>;
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&adv7533_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vcca-supply = <&vreg_l1b_0p925>;
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmss_smmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1461,8 +1461,8 @@
|
|||
<&sleep_clk>,
|
||||
<&gcc GCC_MMSS_GPLL0_CLK>,
|
||||
<&gcc GCC_MMSS_GPLL0_DIV_CLK>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
|
|
@ -1534,7 +1534,7 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1570,7 +1570,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@c994000 {
|
||||
mdss_dsi0: dsi@c994000 {
|
||||
compatible = "qcom,sdm660-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c994000 0x400>;
|
||||
|
|
@ -1584,8 +1584,8 @@
|
|||
|
||||
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>;
|
||||
|
||||
clocks = <&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_BYTE0_CLK>,
|
||||
|
|
@ -1606,7 +1606,7 @@
|
|||
"pixel",
|
||||
"core";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -1616,20 +1616,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@c994400 {
|
||||
mdss_dsi0_phy: phy@c994400 {
|
||||
compatible = "qcom,dsi-phy-14nm-660";
|
||||
reg = <0x0c994400 0x100>,
|
||||
<0x0c994500 0x300>,
|
||||
|
|
|
|||
|
|
@ -148,14 +148,14 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
mdp5_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss {
|
||||
dsi1: dsi@c996000 {
|
||||
mdss_dsi1: dsi@c996000 {
|
||||
compatible = "qcom,sdm660-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c996000 0x400>;
|
||||
|
|
@ -170,8 +170,8 @@
|
|||
|
||||
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
|
||||
<&mmcc PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>;
|
||||
|
||||
clocks = <&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_BYTE1_CLK>,
|
||||
|
|
@ -192,7 +192,7 @@
|
|||
"pixel",
|
||||
"core";
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -202,20 +202,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@c996400 {
|
||||
mdss_dsi1_phy: phy@c996400 {
|
||||
compatible = "qcom,dsi-phy-14nm-660";
|
||||
reg = <0x0c996400 0x100>,
|
||||
<0x0c996500 0x300>,
|
||||
|
|
@ -239,10 +239,10 @@
|
|||
<&sleep_clk>,
|
||||
<&gcc GCC_MMSS_GPLL0_CLK>,
|
||||
<&gcc GCC_MMSS_GPLL0_DIV_CLK>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<0>,
|
||||
<0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1264,6 +1264,7 @@
|
|||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -636,25 +636,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
edp_brij_i2c: &i2c3 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -687,7 +668,7 @@ edp_brij_i2c: &i2c3 {
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
sn65dsi86_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -767,6 +748,25 @@ ap_ts_i2c: &i2c14 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Cheza fw does not properly program the GPU aperture to allow the
|
||||
* GPU to update the SMMU pagetables for context switches. Work
|
||||
|
|
|
|||
|
|
@ -415,53 +415,6 @@
|
|||
firmware-name = "qcom/sdm845/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&dsi1 {
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_b>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi1_phy {
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -517,7 +470,7 @@
|
|||
reg = <0>;
|
||||
|
||||
lt9611_a: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -525,7 +478,7 @@
|
|||
reg = <1>;
|
||||
|
||||
lt9611_b: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
remote-endpoint = <&mdss_dsi1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -556,6 +509,53 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <<9611_b>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi1_phy {
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
|
||||
|
|
@ -685,10 +685,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8998_rradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
|
||||
&q6afedai {
|
||||
dai@22 {
|
||||
|
|
|
|||
|
|
@ -417,80 +417,6 @@
|
|||
firmware-name = "qcom/sdm845/cdsp.mdt";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&truly_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "truly,nt35597-2K-display";
|
||||
reg = <0>;
|
||||
vdda-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
truly_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
truly_in_1: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&dsi1 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi1_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&truly_in_1>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi1_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi1_pll>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -527,6 +453,80 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&truly_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "truly,nt35597-2K-display";
|
||||
reg = <0>;
|
||||
vdda-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
truly_in_0: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
truly_in_1: endpoint {
|
||||
remote-endpoint = <&mdss_dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi1_1p2>;
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&truly_in_1>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi1_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi1_pll>;
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
|
||||
|
|
|
|||
|
|
@ -336,44 +336,6 @@
|
|||
firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
/*
|
||||
* Both devices use different panels but all other properties
|
||||
* are common. Compatible line is declared in device dts.
|
||||
*/
|
||||
display_panel: panel@0 {
|
||||
status = "disabled";
|
||||
|
||||
reg = <0>;
|
||||
|
||||
vddio-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -452,6 +414,44 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
/*
|
||||
* Both devices use different panels but all other properties
|
||||
* are common. Compatible line is declared in device dts.
|
||||
*/
|
||||
display_panel: panel@0 {
|
||||
status = "disabled";
|
||||
|
||||
reg = <0>;
|
||||
|
||||
vddio-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
/* Modem/wifi */
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
|
|
@ -480,7 +480,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8998_rradc {
|
||||
&pmi8998_charger {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
};
|
||||
|
||||
&sound {
|
||||
model = "OnePlus 6";
|
||||
audio-routing = "RX_BIAS", "MCLK",
|
||||
|
|
|
|||
|
|
@ -47,6 +47,10 @@
|
|||
"AMIC5", "MIC BIAS3";
|
||||
};
|
||||
|
||||
&pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The TFA9894 codec is currently unsupported.
|
||||
* We need to delete the node to allow the soundcard
|
||||
|
|
|
|||
|
|
@ -411,44 +411,6 @@
|
|||
firmware-name = "qcom/sdm845/axolotl/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "visionox,rm69299-shift";
|
||||
status = "okay";
|
||||
reg = <0>;
|
||||
vdda-supply = <&vreg_l14a_1p88>;
|
||||
vdd3p3-supply = <&vreg_l28a_3p0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
port {
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -494,6 +456,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
/* SMB1355@0x0C */
|
||||
};
|
||||
|
||||
&ipa {
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
|
|
@ -505,6 +471,44 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "visionox,rm69299-shift";
|
||||
status = "okay";
|
||||
reg = <0>;
|
||||
vdda-supply = <&vreg_l14a_1p88>;
|
||||
vdd3p3-supply = <&vreg_l28a_3p0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
port {
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn";
|
||||
|
|
@ -522,6 +526,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8998_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -368,43 +368,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
status = "okay";
|
||||
|
||||
panel: panel@0 {
|
||||
/* The compatible is assigned in device DTs. */
|
||||
reg = <0>;
|
||||
|
||||
backlight = <&pmi8998_wled>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
vsp-supply = <&lab>;
|
||||
vsn-supply = <&ibb>;
|
||||
panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
|
||||
pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
vdds-supply = <&vreg_l1a_0p9>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -515,6 +478,43 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
status = "okay";
|
||||
|
||||
panel: panel@0 {
|
||||
/* The compatible is assigned in device DTs. */
|
||||
reg = <0>;
|
||||
|
||||
backlight = <&pmi8998_wled>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
vsp-supply = <&lab>;
|
||||
vsn-supply = <&ibb>;
|
||||
panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
|
||||
touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
|
||||
pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vdds-supply = <&vreg_l1a_0p9>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8998_gpios {
|
||||
focus_n: focus-n-state {
|
||||
pins = "gpio2";
|
||||
|
|
|
|||
|
|
@ -115,6 +115,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
battery: battery {
|
||||
compatible = "simple-battery";
|
||||
|
||||
charge-full-design-microamp-hours = <4000000>;
|
||||
voltage-min-design-microvolt = <3400000>;
|
||||
voltage-max-design-microvolt = <4400000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: vreg-s4a-1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
|
|
@ -223,39 +231,6 @@
|
|||
firmware-name = "qcom/sdm845/beryllium/cdsp.mbn";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
display_panel: panel@0 {
|
||||
reg = <0>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
backlight = <&pmi8998_wled>;
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -298,6 +273,39 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
display_panel: panel@0 {
|
||||
reg = <0>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
backlight = <&pmi8998_wled>;
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn";
|
||||
|
|
@ -341,12 +349,14 @@
|
|||
qcom,cabc;
|
||||
};
|
||||
|
||||
&pm8998_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
&pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmi8998_rradc {
|
||||
&pm8998_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -373,44 +373,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
status = "okay";
|
||||
|
||||
display_panel: panel@0 {
|
||||
compatible = "jdi,fhd-nt35596s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
backlight = <&pmi8998_wled>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sde_dsi_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -505,6 +467,44 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
status = "okay";
|
||||
|
||||
display_panel: panel@0 {
|
||||
compatible = "jdi,fhd-nt35596s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
|
||||
vddio-supply = <&vreg_l14a_1p8>;
|
||||
backlight = <&pmi8998_wled>;
|
||||
vddpos-supply = <&lab>;
|
||||
vddneg-supply = <&ibb>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sde_dsi_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -4501,14 +4501,14 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4608,7 +4608,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@ae94000 {
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sdm845-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae94000 0 0x400>;
|
||||
|
|
@ -4630,12 +4630,12 @@
|
|||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -4648,20 +4648,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
mdss_dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0 0x0ae94400 0 0x200>,
|
||||
<0 0x0ae94600 0 0x280>,
|
||||
|
|
@ -4680,7 +4680,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi1: dsi@ae96000 {
|
||||
mdss_dsi1: dsi@ae96000 {
|
||||
compatible = "qcom,sdm845-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae96000 0 0x400>;
|
||||
|
|
@ -4702,12 +4702,12 @@
|
|||
"iface",
|
||||
"bus";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -4720,20 +4720,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
mdss_dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0 0x0ae96400 0 0x200>,
|
||||
<0 0x0ae96600 0 0x280>,
|
||||
|
|
@ -4895,10 +4895,10 @@
|
|||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
|
|
@ -5129,6 +5129,7 @@
|
|||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -311,25 +311,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -422,7 +403,7 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
sn65dsi86_in_a: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -475,6 +456,25 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdx75.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SDX75 IDP";
|
||||
compatible = "qcom,sdx75-idp", "qcom,sdx75";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
};
|
||||
|
||||
&chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <110 6>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,670 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* SDX75 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
chosen: chosen { };
|
||||
|
||||
clocks {
|
||||
xo_board: xo-board {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <76800000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
next-level-cache = <&L2_0>;
|
||||
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
next-level-cache = <&L2_100>;
|
||||
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
next-level-cache = <&L2_200>;
|
||||
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <100>;
|
||||
next-level-cache = <&L2_300>;
|
||||
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_OFF: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
entry-latency-us = <235>;
|
||||
exit-latency-us = <428>;
|
||||
min-residency-us = <1774>;
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
local-timer-stop;
|
||||
};
|
||||
|
||||
CPU_RAIL_OFF: cpu-rail-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <750>;
|
||||
min-residency-us = <4090>;
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
local-timer-stop;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41000044>;
|
||||
entry-latency-us = <1050>;
|
||||
exit-latency-us = <2500>;
|
||||
min-residency-us = <5309>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41001344>;
|
||||
entry-latency-us = <2761>;
|
||||
exit-latency-us = <3964>;
|
||||
min-residency-us = <8467>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_2: cluster-sleep-2 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x4100b344>;
|
||||
entry-latency-us = <2793>;
|
||||
exit-latency-us = <4023>;
|
||||
min-residency-us = <9826>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scm: scm {
|
||||
compatible = "qcom,scm-sdx75", "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x0>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cpu-cluster0 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gunyah_hyp_mem: gunyah-hyp@80000000 {
|
||||
reg = <0x0 0x80000000 0x0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
hyp_elf_package_mem: hyp-elf-package@80800000 {
|
||||
reg = <0x0 0x80800000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
access_control_db_mem: access-control-db@81380000 {
|
||||
reg = <0x0 0x81380000 0x0 0x80000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qteetz_mem: qteetz@814e0000 {
|
||||
reg = <0x0 0x814e0000 0x0 0x2a0000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
trusted_apps_mem: trusted-apps@81780000 {
|
||||
reg = <0x0 0x81780000 0x0 0xa00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
xbl_ramdump_mem: xbl-ramdump@87a00000 {
|
||||
reg = <0x0 0x87a00000 0x0 0x1c0000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
cpucp_fw_mem: cpucp-fw@87c00000 {
|
||||
reg = <0x0 0x87c00000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
xbl_dtlog_mem: xbl-dtlog@87d00000 {
|
||||
reg = <0x0 0x87d00000 0x0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
xbl_sc_mem: xbl-sc@87d40000 {
|
||||
reg = <0x0 0x87d40000 0x0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
modem_efs_shared_mem: modem-efs-shared@87d80000 {
|
||||
reg = <0x0 0x87d80000 0x0 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
aop_image_mem: aop-image@87e00000 {
|
||||
reg = <0x0 0x87e00000 0x0 0x20000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
smem_mem: smem@87e20000 {
|
||||
reg = <0x0 0x87e20000 0x0 0xc0000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
aop_cmd_db_mem: aop-cmd-db@87ee0000 {
|
||||
compatible = "qcom,cmd-db";
|
||||
reg = <0x0 0x87ee0000 0x0 0x20000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
aop_config_mem: aop-config@87f00000 {
|
||||
reg = <0x0 0x87f00000 0x0 0x20000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_fw_mem: ipa-fw@87f20000 {
|
||||
reg = <0x0 0x87f20000 0x0 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secdata_mem: secdata@87f30000 {
|
||||
reg = <0x0 0x87f30000 0x0 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tme_crashdump_mem: tme-crashdump@87f31000 {
|
||||
reg = <0x0 0x87f31000 0x0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tme_log_mem: tme-log@87f71000 {
|
||||
reg = <0x0 0x87f71000 0x0 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
uefi_log_mem: uefi-log@87f75000 {
|
||||
reg = <0x0 0x87f75000 0x0 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qdss_mem: qdss@88800000 {
|
||||
reg = <0x0 0x88800000 0x0 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
audio_heap_mem: audio-heap@88b00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x88b00000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
|
||||
reg = <0x0 0x88f00000 0x0 0x5080000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
|
||||
reg = <0x0 0x8df80000 0x0 0x80000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpssadsp_mem: mpssadsp@8e000000 {
|
||||
reg = <0x0 0x8e000000 0x0 0xf400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
|
||||
reg = <0x0 0xbdb00000 0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
|
||||
reg = <0x0 0xbfb00000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
|
||||
reg = <0x0 0xbfc00000 0x0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
smem: qcom,smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0 0 0 0x10 0>;
|
||||
dma-ranges = <0 0 0 0 0x10 0>;
|
||||
|
||||
gcc: clock-controller@80000 {
|
||||
compatible = "qcom,sdx75-gcc";
|
||||
reg = <0x0 0x0080000 0x0 0x1f7400>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qupv3_id_0: geniqup@9c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x009c0000 0x0 0x2000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
clock-names = "m-ahb",
|
||||
"s-ahb";
|
||||
iommus = <&apps_smmu 0xe3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
uart1: serial@984000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0x0 0x00984000 0x0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&qupv3_se1_2uart_active>;
|
||||
pinctrl-1 = <&qupv3_se1_2uart_sleep>;
|
||||
pinctrl-names = "default",
|
||||
"sleep";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
reg = <0x0 0x01f40000 0x0 0x40000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sdx75-pdc", "qcom,pdc";
|
||||
reg = <0x0 0xb220000 0x0 0x30000>,
|
||||
<0x0 0x174000f0 0x0 0x64>;
|
||||
qcom,pdc-ranges = <0 147 52>,
|
||||
<52 266 32>,
|
||||
<84 500 59>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
tlmm: pinctrl@f000000 {
|
||||
compatible = "qcom,sdx75-tlmm";
|
||||
reg = <0x0 0x0f000000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 133>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
|
||||
tx-pins {
|
||||
pins = "gpio12";
|
||||
function = "qup_se1_l2_mira";
|
||||
drive-strength= <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pins = "gpio13";
|
||||
function = "qup_se1_l3_mira";
|
||||
drive-strength= <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
||||
reg = <0x0 0x15000000 0x0 0x40000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
reg = <0x0 0x17200000 0x0 0x10000>,
|
||||
<0x0 0x17260000 0x0 0x80000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@17420000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0 0x17420000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x20000000>;
|
||||
|
||||
frame@17421000 {
|
||||
reg = <0x17421000 0x1000>,
|
||||
<0x17422000 0x1000>;
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
frame@17423000 {
|
||||
reg = <0x17423000 0x1000>;
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17425000 {
|
||||
reg = <0x17425000 0x1000>;
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17427000 {
|
||||
reg = <0x17427000 0x1000>;
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17429000 {
|
||||
reg = <0x17429000 0x1000>;
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@1742b000 {
|
||||
reg = <0x1742b000 0x1000>;
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@1742d000 {
|
||||
reg = <0x1742d000 0x1000>;
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
apps_rsc: rsc@17a00000 {
|
||||
label = "apps_rsc";
|
||||
compatible = "qcom,rpmh-rsc";
|
||||
reg = <0x0 0x17a00000 0x0 0x10000>,
|
||||
<0x0 0x17a10000 0x0 0x10000>,
|
||||
<0x0 0x17a20000 0x0 0x10000>;
|
||||
reg-names = "drv-0", "drv-1", "drv-2";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 3>,
|
||||
<SLEEP_TCS 2>,
|
||||
<WAKE_TCS 2>,
|
||||
<CONTROL_TCS 0>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
};
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sdx75-rpmh-clk";
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@17d91000 {
|
||||
compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
|
||||
reg = <0x0 0x17d91000 0x0 0x1000>;
|
||||
reg-names = "freq-domain0";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GPLL0>;
|
||||
clock-names = "xo",
|
||||
"alternate";
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dcvsh-irq-0";
|
||||
#freq-domain-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
|
@ -56,6 +56,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -82,6 +84,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -104,6 +108,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -126,6 +132,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -148,6 +156,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -170,6 +180,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -192,6 +204,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -214,6 +228,8 @@
|
|||
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -257,6 +273,76 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_PC: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41000044>;
|
||||
entry-latency-us = <2752>;
|
||||
exit-latency-us = <3048>;
|
||||
min-residency-us = <6118>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41001244>;
|
||||
entry-latency-us = <3638>;
|
||||
exit-latency-us = <4562>;
|
||||
min-residency-us = <8467>;
|
||||
};
|
||||
|
||||
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x4100b244>;
|
||||
entry-latency-us = <3263>;
|
||||
exit-latency-us = <6562>;
|
||||
min-residency-us = <9987>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_idle_states: idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
entry-latency-us = <549>;
|
||||
exit-latency-us = <901>;
|
||||
min-residency-us = <1774>;
|
||||
local-timer-stop;
|
||||
};
|
||||
|
||||
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
entry-latency-us = <702>;
|
||||
exit-latency-us = <915>;
|
||||
min-residency-us = <4001>;
|
||||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
entry-latency-us = <523>;
|
||||
exit-latency-us = <1244>;
|
||||
min-residency-us = <2207>;
|
||||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
entry-latency-us = <526>;
|
||||
exit-latency-us = <1854>;
|
||||
min-residency-us = <5555>;
|
||||
local-timer-stop;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
|
@ -378,6 +464,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_opp_table: opp-table-qup {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-75000000 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-128000000 {
|
||||
opp-hz = /bits/ 64 <128000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
@ -386,6 +491,61 @@
|
|||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD4: power-domain-cpu4 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD5: power-domain-cpu5 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD6: power-domain-cpu6 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU_PD7: power-domain-cpu7 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cpu-cluster0 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_PC
|
||||
&CLUSTER_SLEEP_CX_RET
|
||||
&CLUSTER_AOSS_SLEEP>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
|
|
@ -741,6 +901,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@884000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00884000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM6350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@888000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00888000 0 0x4000>;
|
||||
|
|
@ -1726,6 +1902,34 @@
|
|||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_uart1_cts: qup-uart1-cts-default-state {
|
||||
pins = "gpio61";
|
||||
function = "qup01";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_uart1_rts: qup-uart1-rts-default-state {
|
||||
pins = "gpio62";
|
||||
function = "qup01";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_uart1_rx: qup-uart1-rx-default-state {
|
||||
pins = "gpio64";
|
||||
function = "qup01";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_uart1_tx: qup-uart1-tx-default-state {
|
||||
pins = "gpio63";
|
||||
function = "qup01";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
|
|
@ -1905,6 +2109,7 @@
|
|||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>, <CONTROL_TCS 1>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sm6350-rpmh-clk";
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
|
||||
#include <dt-bindings/dma/qcom-gpi.h>
|
||||
#include <dt-bindings/firmware/qcom,scm.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
|
@ -1258,6 +1259,42 @@
|
|||
};
|
||||
};
|
||||
|
||||
adreno_smmu: iommu@5940000 {
|
||||
compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0 0x05940000 0 0x10000>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
||||
clock-names = "bus";
|
||||
|
||||
power-domains = <&gpucc GPU_CX_GDSC>;
|
||||
};
|
||||
|
||||
gpucc: clock-controller@5990000 {
|
||||
compatible = "qcom,sm6375-gpucc";
|
||||
reg = <0 0x05990000 0 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
|
||||
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
|
||||
power-domains = <&rpmpd SM6375_VDDGX>;
|
||||
required-opps = <&rpmpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
remoteproc_mss: remoteproc@6000000 {
|
||||
compatible = "qcom,sm6375-mpss-pas";
|
||||
reg = <0 0x06000000 0 0x4040>;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
aliases {
|
||||
serial0 = &uart9;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -524,6 +525,39 @@
|
|||
};
|
||||
};
|
||||
|
||||
&qup_uart1_cts {
|
||||
/*
|
||||
* Configure a bias-bus-hold on CTS to lower power
|
||||
* usage when Bluetooth is turned off. Bus hold will
|
||||
* maintain a low power state regardless of whether
|
||||
* the Bluetooth module drives the pin in either
|
||||
* direction or leaves the pin fully unpowered.
|
||||
*/
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
&qup_uart1_rts {
|
||||
/* We'll drive RTS, so no pull */
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
&qup_uart1_rx {
|
||||
/*
|
||||
* Configure a pull-up on RX. This is needed to avoid
|
||||
* garbage data when the TX pin of the Bluetooth module is
|
||||
* in tri-state (module powered off or not driving the
|
||||
* signal yet).
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
&qup_uart1_tx {
|
||||
/* We'll drive TX, so no pull */
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -561,6 +595,75 @@
|
|||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <13 4>, <56 2>;
|
||||
|
||||
qup_uart1_sleep_cts: qup-uart1-sleep-cts-state {
|
||||
pins = "gpio61";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure a bias-bus-hold on CTS to lower power
|
||||
* usage when Bluetooth is turned off. Bus hold will
|
||||
* maintain a low power state regardless of whether
|
||||
* the Bluetooth module drives the pin in either
|
||||
* direction or leaves the pin fully unpowered.
|
||||
*/
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
qup_uart1_sleep_rts: qup-uart1-sleep-rts-state {
|
||||
pins = "gpio62";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure pull-down on RTS. As RTS is active low
|
||||
* signal, pull it low to indicate the BT SoC that it
|
||||
* can wakeup the system anytime from suspend state by
|
||||
* pulling RX low (by sending wakeup bytes).
|
||||
*/
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_uart1_sleep_rx: qup-uart1-sleep-rx-state {
|
||||
pins = "gpio64";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure a pull-up on RX. This is needed to avoid
|
||||
* garbage data when the TX pin of the Bluetooth module
|
||||
* is floating which may cause spurious wakeups.
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_uart1_sleep_tx: qup-uart1-sleep-tx-state {
|
||||
pins = "gpio63";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure pull-up on TX when it isn't actively driven
|
||||
* to prevent BT SoC from receiving garbage during sleep.
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
/delete-property/ interrupts;
|
||||
interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 64 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-1 = <&qup_uart1_sleep_cts>, <&qup_uart1_sleep_rts>, <&qup_uart1_sleep_tx>, <&qup_uart1_sleep_rx>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn3988-bt";
|
||||
|
||||
vddio-supply = <&vreg_l11a>;
|
||||
vddxo-supply = <&vreg_l7a>;
|
||||
vddrf-supply = <&vreg_l2e>;
|
||||
vddch0-supply = <&vreg_l10e>;
|
||||
swctrl-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
|
|
|
|||
|
|
@ -55,8 +55,8 @@
|
|||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -82,8 +82,8 @@
|
|||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -105,8 +105,8 @@
|
|||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -128,8 +128,8 @@
|
|||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -151,8 +151,8 @@
|
|||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -174,8 +174,8 @@
|
|||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -197,8 +197,8 @@
|
|||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -220,8 +220,8 @@
|
|||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
operating-points-v2 = <&cpu7_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
|
|
@ -1751,49 +1751,49 @@
|
|||
config_noc: interconnect@1500000 {
|
||||
compatible = "qcom,sm8150-config-noc";
|
||||
reg = <0 0x01500000 0 0x7400>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system_noc: interconnect@1620000 {
|
||||
compatible = "qcom,sm8150-system-noc";
|
||||
reg = <0 0x01620000 0 0x19400>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect@163a000 {
|
||||
compatible = "qcom,sm8150-mc-virt";
|
||||
reg = <0 0x0163a000 0 0x1000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,sm8150-aggre1-noc";
|
||||
reg = <0 0x016e0000 0 0xd080>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
compatible = "qcom,sm8150-aggre2-noc";
|
||||
reg = <0 0x01700000 0 0x20000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
compute_noc: interconnect@1720000 {
|
||||
compatible = "qcom,sm8150-compute-noc";
|
||||
reg = <0 0x01720000 0 0x7000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1740000 {
|
||||
compatible = "qcom,sm8150-mmss-noc";
|
||||
reg = <0 0x01740000 0 0x1c100>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
|
|
@ -2111,7 +2111,7 @@
|
|||
<&apps_smmu 0x506 0x0011>,
|
||||
<&apps_smmu 0x508 0x0011>,
|
||||
<&apps_smmu 0x512 0x0000>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "memory";
|
||||
};
|
||||
|
||||
|
|
@ -3538,14 +3538,14 @@
|
|||
dc_noc: interconnect@9160000 {
|
||||
compatible = "qcom,sm8150-dc-noc";
|
||||
reg = <0 0x09160000 0 0x3200>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@9680000 {
|
||||
compatible = "qcom,sm8150-gem-noc";
|
||||
reg = <0 0x09680000 0 0x3e200>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
|
|
@ -3586,6 +3586,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
|
|
@ -3635,6 +3639,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_2_dwc3: usb@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
|
|
@ -3650,7 +3658,7 @@
|
|||
camnoc_virt: interconnect@ac00000 {
|
||||
compatible = "qcom,sm8150-camnoc-virt";
|
||||
reg = <0 0x0ac00000 0 0x1000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
|
|
@ -3659,8 +3667,8 @@
|
|||
reg = <0 0x0ae00000 0 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
|
@ -4325,7 +4333,7 @@
|
|||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@18323000 {
|
||||
|
|
|
|||
|
|
@ -26,9 +26,10 @@
|
|||
framebuffer: framebuffer@9c000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0x9c000000 0 0x2300000>;
|
||||
width = <1644>;
|
||||
height = <3840>;
|
||||
stride = <(1644 * 4)>;
|
||||
/* pdx203 BL initializes in 2.5k mode, not 4k */
|
||||
width = <1096>;
|
||||
height = <2560>;
|
||||
stride = <(1096 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
/*
|
||||
* That's a lot of clocks, but it's necessary due
|
||||
|
|
|
|||
|
|
@ -470,75 +470,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,sync-dual-dsi;
|
||||
qcom,master-dsi;
|
||||
status = "okay";
|
||||
|
||||
display_panel: panel@0 {
|
||||
reg = <0>;
|
||||
vddio-supply = <&vreg_l14a_1p88>;
|
||||
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&backlight>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1{
|
||||
reg = <1>;
|
||||
|
||||
panel_in_1: endpoint {
|
||||
remote-endpoint = <&dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
data-lanes = <0 1 2>;
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
phy-type = <PHY_TYPE_CPHY>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi1 {
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,sync-dual-dsi;
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi1_out {
|
||||
data-lanes = <0 1 2>;
|
||||
remote-endpoint = <&panel_in_1>;
|
||||
};
|
||||
|
||||
&dsi1_phy {
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
phy-type = <PHY_TYPE_CPHY>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -607,6 +538,75 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,sync-dual-dsi;
|
||||
qcom,master-dsi;
|
||||
status = "okay";
|
||||
|
||||
display_panel: panel@0 {
|
||||
reg = <0>;
|
||||
vddio-supply = <&vreg_l14a_1p88>;
|
||||
reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&backlight>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
panel_in_0: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1{
|
||||
reg = <1>;
|
||||
|
||||
panel_in_1: endpoint {
|
||||
remote-endpoint = <&mdss_dsi1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0_out {
|
||||
data-lanes = <0 1 2>;
|
||||
remote-endpoint = <&panel_in_0>;
|
||||
};
|
||||
|
||||
&mdss_dsi0_phy {
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
phy-type = <PHY_TYPE_CPHY>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-supply = <&vreg_l9a_1p2>;
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,sync-dual-dsi;
|
||||
/* DSI1 is slave, so use DSI0 clocks */
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dsi1_out {
|
||||
data-lanes = <0 1 2>;
|
||||
remote-endpoint = <&panel_in_1>;
|
||||
};
|
||||
|
||||
&mdss_dsi1_phy {
|
||||
vdds-supply = <&vreg_l5a_0p88>;
|
||||
phy-type = <PHY_TYPE_CPHY>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -106,8 +106,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -137,8 +137,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -162,8 +162,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -187,8 +187,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -212,8 +212,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -237,8 +237,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -262,8 +262,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -287,8 +287,8 @@
|
|||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
operating-points-v2 = <&cpu7_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -1789,49 +1789,49 @@
|
|||
config_noc: interconnect@1500000 {
|
||||
compatible = "qcom,sm8250-config-noc";
|
||||
reg = <0 0x01500000 0 0xa580>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system_noc: interconnect@1620000 {
|
||||
compatible = "qcom,sm8250-system-noc";
|
||||
reg = <0 0x01620000 0 0x1c200>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mc_virt: interconnect@163d000 {
|
||||
compatible = "qcom,sm8250-mc-virt";
|
||||
reg = <0 0x0163d000 0 0x1000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,sm8250-aggre1-noc";
|
||||
reg = <0 0x016e0000 0 0x1f180>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre2_noc: interconnect@1700000 {
|
||||
compatible = "qcom,sm8250-aggre2-noc";
|
||||
reg = <0 0x01700000 0 0x33000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
compute_noc: interconnect@1733000 {
|
||||
compatible = "qcom,sm8250-compute-noc";
|
||||
reg = <0 0x01733000 0 0xa180>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1740000 {
|
||||
compatible = "qcom,sm8250-mmss-noc";
|
||||
reg = <0 0x01740000 0 0x1f080>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
|
|
@ -2260,7 +2260,7 @@
|
|||
<&apps_smmu 0x59f 0x0000>,
|
||||
<&apps_smmu 0x586 0x0011>,
|
||||
<&apps_smmu 0x596 0x0011>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "memory";
|
||||
};
|
||||
|
||||
|
|
@ -3693,21 +3693,21 @@
|
|||
dc_noc: interconnect@90c0000 {
|
||||
compatible = "qcom,sm8250-dc-noc";
|
||||
reg = <0 0x090c0000 0 0x4200>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@9100000 {
|
||||
compatible = "qcom,sm8250-gem-noc";
|
||||
reg = <0 0x09100000 0 0xb4000>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
npu_noc: interconnect@9990000 {
|
||||
compatible = "qcom,sm8250-npu-noc";
|
||||
reg = <0 0x09990000 0 0x1600>;
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
|
|
@ -3750,6 +3750,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
|
|
@ -3810,6 +3814,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_2_dwc3: usb@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
|
|
@ -3837,8 +3845,8 @@
|
|||
<&videocc VIDEO_CC_MVS0_CLK>;
|
||||
clock-names = "iface", "core", "vcodec0_core";
|
||||
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
|
||||
<&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
|
||||
<&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "cpu-cfg", "video-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x2100 0x0400>;
|
||||
|
|
@ -4122,10 +4130,10 @@
|
|||
<&apps_smmu 0xc40 0x400>,
|
||||
<&apps_smmu 0xc41 0x400>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
|
||||
<&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
|
||||
<&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "cam_ahb",
|
||||
"cam_hf_0_mnoc",
|
||||
"cam_sf_0_mnoc",
|
||||
|
|
@ -4182,8 +4190,8 @@
|
|||
reg = <0 0x0ae00000 0 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
|
@ -4234,14 +4242,14 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4271,7 +4279,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@ae94000 {
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sm8250-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae94000 0 0x400>;
|
||||
|
|
@ -4294,12 +4302,12 @@
|
|||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -4312,14 +4320,14 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
mdss_dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -4344,7 +4352,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
mdss_dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0 0x0ae94400 0 0x200>,
|
||||
<0 0x0ae94600 0 0x280>,
|
||||
|
|
@ -4363,7 +4371,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi1: dsi@ae96000 {
|
||||
mdss_dsi1: dsi@ae96000 {
|
||||
compatible = "qcom,sm8250-dsi-ctrl",
|
||||
"qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae96000 0 0x400>;
|
||||
|
|
@ -4386,12 +4394,12 @@
|
|||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -4404,20 +4412,20 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
mdss_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
mdss_dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0 0x0ae96400 0 0x200>,
|
||||
<0 0x0ae96600 0 0x280>,
|
||||
|
|
@ -4443,10 +4451,10 @@
|
|||
power-domains = <&rpmhpd SM8250_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
|
|
@ -5671,7 +5679,7 @@
|
|||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#interconnect-cells = <1>;
|
||||
#interconnect-cells = <2>;
|
||||
};
|
||||
|
||||
cpufreq_hw: cpufreq@18591000 {
|
||||
|
|
|
|||
|
|
@ -424,10 +424,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mpss {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8350/modem.mbn";
|
||||
|
|
|
|||
|
|
@ -2295,6 +2295,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
|
|
@ -2364,6 +2368,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_2_dwc3: usb@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
|
|
|
|||
|
|
@ -568,10 +568,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
max-link-speed = <2>;
|
||||
|
|
|
|||
|
|
@ -4297,6 +4297,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
|
|
|
|||
|
|
@ -87,6 +87,87 @@
|
|||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
|
||||
model = "SM8550-MTP";
|
||||
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"VA DMIC0", "MIC BIAS1",
|
||||
"VA DMIC1", "MIC BIAS1",
|
||||
"VA DMIC2", "MIC BIAS3",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "MIC BIAS2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX SWR_ADC1", "ADC2_OUTPUT";
|
||||
|
||||
wcd-playback-dai-link {
|
||||
link-name = "WCD Playback";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
wcd-capture-dai-link {
|
||||
link-name = "WCD Capture";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
wsa-dai-link {
|
||||
link-name = "WSA Playback";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
va-dai-link {
|
||||
link-name = "VA Capture";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&lpass_vamacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
|
|
@ -419,6 +500,24 @@
|
|||
};
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
spkr_2_sd_n_active: spkr-2-sd-n-active-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -553,6 +652,36 @@
|
|||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
status = "okay";
|
||||
|
||||
/* WSA8845 */
|
||||
left_spkr: speaker@0,0 {
|
||||
compatible = "sdw20217020400";
|
||||
reg = <0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spkr_1_sd_n_active>;
|
||||
powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l3g_1p2>;
|
||||
};
|
||||
|
||||
/* WSA8845 */
|
||||
right_spkr: speaker@0,1 {
|
||||
compatible = "sdw20217020400";
|
||||
reg = <0 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spkr_2_sd_n_active>;
|
||||
powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SpkrRight";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l3g_1p2>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,22 @@
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&volume_up_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
key-volume-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -88,6 +104,87 @@
|
|||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
|
||||
model = "SM8550-QRD";
|
||||
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"VA DMIC0", "MIC BIAS1",
|
||||
"VA DMIC1", "MIC BIAS1",
|
||||
"VA DMIC2", "MIC BIAS3",
|
||||
"TX DMIC0", "MIC BIAS1",
|
||||
"TX DMIC1", "MIC BIAS2",
|
||||
"TX DMIC2", "MIC BIAS3",
|
||||
"TX SWR_ADC1", "ADC2_OUTPUT";
|
||||
|
||||
wcd-playback-dai-link {
|
||||
link-name = "WCD Playback";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
wcd-capture-dai-link {
|
||||
link-name = "WCD Capture";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
wsa-dai-link {
|
||||
link-name = "WSA Playback";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
|
||||
va-dai-link {
|
||||
link-name = "VA Capture";
|
||||
|
||||
cpu {
|
||||
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&lpass_vamacro 0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6apm>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
|
|
@ -431,6 +528,24 @@
|
|||
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
spkr_2_sd_n_active: spkr-2-sd-n-active-state {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -516,11 +631,58 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pm8550_gpios {
|
||||
volume_up_n: volume-up-n-state {
|
||||
pins = "gpio6";
|
||||
function = "normal";
|
||||
power-source = <1>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550_pwm {
|
||||
status = "okay";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm8550b_eusb2_repeater {
|
||||
vdd18-supply = <&vreg_l15b_1p8>;
|
||||
vdd3-supply = <&vreg_l5b_3p1>;
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_1_phy_aux_clk {
|
||||
clock-frequency = <1000>;
|
||||
};
|
||||
|
|
@ -551,6 +713,36 @@
|
|||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
status = "okay";
|
||||
|
||||
/* WSA8845, Speaker North */
|
||||
north_spkr: speaker@0,0 {
|
||||
compatible = "sdw20217020400";
|
||||
reg = <0 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spkr_1_sd_n_active>;
|
||||
powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l3g_1p2>;
|
||||
};
|
||||
|
||||
/* WSA8845, Speaker South */
|
||||
south_spkr: speaker@0,1 {
|
||||
compatible = "sdw20217020400";
|
||||
reg = <0 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spkr_2_sd_n_active>;
|
||||
powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SpkrRight";
|
||||
vdd-1p8-supply = <&vreg_l15b_1p8>;
|
||||
vdd-io-supply = <&vreg_l3g_1p2>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -2486,6 +2486,13 @@
|
|||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&mdss_dp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
|
|
@ -2513,6 +2520,84 @@
|
|||
};
|
||||
};
|
||||
|
||||
mdss_dp0: displayport-controller@ae90000 {
|
||||
compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
|
||||
reg = <0 0xae90000 0 0x200>,
|
||||
<0 0xae90200 0 0x200>,
|
||||
<0 0xae90400 0 0xc00>,
|
||||
<0 0xae91000 0 0x400>,
|
||||
<0 0xae91400 0 0x400>;
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8550_MMCX>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdss_dp0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdss_dp0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-162000000 {
|
||||
opp-hz = /bits/ 64 <162000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0 0x0ae94000 0 0x400>;
|
||||
|
|
@ -2696,8 +2781,8 @@
|
|||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<0>, /* dp0 */
|
||||
<0>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<0>, /* dp1 */
|
||||
<0>,
|
||||
<0>, /* dp2 */
|
||||
|
|
@ -2784,6 +2869,10 @@
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
|
|
@ -3612,6 +3701,7 @@
|
|||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
|
||||
<WAKE_TCS 2>, <CONTROL_TCS 0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
@ -3640,15 +3730,15 @@
|
|||
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_lov_svs_d2: opp-52 {
|
||||
rpmhpd_opp_low_svs_d2: opp-52 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_lov_svs_d1: opp-56 {
|
||||
rpmhpd_opp_low_svs_d1: opp-56 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
||||
};
|
||||
|
||||
rpmhpd_opp_lov_svs_d0: opp-60 {
|
||||
rpmhpd_opp_low_svs_d0: opp-60 {
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
||||
};
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue