wl18xx: change board type enum according to new FW
Add more board types and remove a now unneeded write to SCR_PAD2 setting the board type. Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
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05057c0621
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@ -45,12 +45,6 @@
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static char *ht_mode_param;
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static char *board_type_param;
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static const u32 wl18xx_board_type_to_scrpad2[NUM_BOARD_TYPES] = {
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[BOARD_TYPE_FPGA_18XX] = SCR_PAD2_BOARD_TYPE_FPGA,
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[BOARD_TYPE_HDK_18XX] = SCR_PAD2_BOARD_TYPE_HDK,
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[BOARD_TYPE_DVP_EVB_18XX] = SCR_PAD2_BOARD_TYPE_DVP_EVB,
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};
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static const u8 wl18xx_rate_to_idx_2ghz[] = {
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/* MCS rates are used only with 11n */
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15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
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@ -604,13 +598,8 @@ out:
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static void wl18xx_set_clk(struct wl1271 *wl)
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{
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struct wl18xx_priv *priv = wl->priv;
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u32 clk_freq;
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/* write the translated board type to SCR_PAD2 */
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wl1271_write32(wl, WL18XX_SCR_PAD2,
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wl18xx_board_type_to_scrpad2[priv->board_type]);
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wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
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/* TODO: PG2: apparently we need to read the clk type */
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@ -1046,21 +1035,22 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
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sizeof(wl18xx_mimo_ht_cap));
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if (!board_type_param) {
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board_type_param = kstrdup("dvp_evb", GFP_KERNEL);
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priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
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board_type_param = kstrdup("dvp", GFP_KERNEL);
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priv->board_type = BOARD_TYPE_DVP_18XX;
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} else if (!strcmp(board_type_param, "fpga")) {
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priv->board_type = BOARD_TYPE_FPGA_18XX;
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} else if (!strcmp(board_type_param, "hdk")) {
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priv->board_type = BOARD_TYPE_HDK_18XX;
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} else if (!strcmp(board_type_param, "dvp")) {
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priv->board_type = BOARD_TYPE_DVP_18XX;
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} else if (!strcmp(board_type_param, "evb")) {
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priv->board_type = BOARD_TYPE_EVB_18XX;
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} else if (!strcmp(board_type_param, "com8")) {
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priv->board_type = BOARD_TYPE_COM8_18XX;
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} else {
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if (!strcmp(board_type_param, "fpga"))
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priv->board_type = BOARD_TYPE_FPGA_18XX;
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else if (!strcmp(board_type_param, "hdk"))
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priv->board_type = BOARD_TYPE_HDK_18XX;
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else if (!strcmp(board_type_param, "dvp_evb"))
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priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
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else {
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wl1271_error("invalid board type '%s'",
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board_type_param);
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wlcore_free_hw(wl);
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return -EINVAL;
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}
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wl1271_error("invalid board type '%s'", board_type_param);
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wlcore_free_hw(wl);
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return -EINVAL;
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}
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wl18xx_conf_init(wl);
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@ -1100,7 +1090,8 @@ module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
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MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
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module_param_named(board_type, board_type_param, charp, S_IRUSR);
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MODULE_PARM_DESC(board_type, "Board type: fpga, hdk or dvp_evb (default)");
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MODULE_PARM_DESC(board_type, "Board type: fpga, hdk, evb, com8 or "
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"dvp (default)");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
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@ -176,20 +176,15 @@ enum {
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};
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enum {
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BOARD_TYPE_FPGA_18XX = 0,
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BOARD_TYPE_HDK_18XX = 1,
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BOARD_TYPE_DVP_EVB_18XX = 2,
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BOARD_TYPE_EVB_18XX = 0,
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BOARD_TYPE_DVP_18XX = 1,
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BOARD_TYPE_HDK_18XX = 2,
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BOARD_TYPE_FPGA_18XX = 3,
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BOARD_TYPE_COM8_18XX = 4,
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NUM_BOARD_TYPES,
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};
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/* board type values used by the firmware in the SCR_PAD2 register */
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enum {
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SCR_PAD2_BOARD_TYPE_FPGA = 0xB1,
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SCR_PAD2_BOARD_TYPE_HDK = 0xB2,
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SCR_PAD2_BOARD_TYPE_DVP_EVB = 0xB3,
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};
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struct wl18xx_mac_and_phy_params {
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u8 phy_standalone;
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u8 rdl;
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