power: supply: bq27xxx: Enable data memory update for certain chips
Support data memory update on BQ27425. Parameters from TI datasheets are also provided for BQ27500, 545, 421, 441, 621; however these are commented out, as they are not tested. Add BQ27XXX_O_CFGUP & _O_RAM for use in bq27xxx_chip_data[n].opts and by data memory update functions. Signed-off-by: Liam Breck <kernel@networkimprov.net> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
This commit is contained in:
Liam Breck
Sebastian Reichel
parent
3a731c6414
commit
05045379b2
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@ -58,8 +58,6 @@
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#include <linux/power/bq27xxx_battery.h>
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#define DRIVER_VERSION "1.2.0"
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#define BQ27XXX_MANUFACTURER "Texas Instruments"
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/* BQ27XXX Flags */
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@ -785,46 +783,138 @@ static enum power_supply_property bq27421_props[] = {
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#define bq27441_props bq27421_props
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#define bq27621_props bq27421_props
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struct bq27xxx_dm_reg {
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u8 subclass_id;
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u8 offset;
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u8 bytes;
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u16 min, max;
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};
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enum bq27xxx_dm_reg_id {
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BQ27XXX_DM_DESIGN_CAPACITY = 0,
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BQ27XXX_DM_DESIGN_ENERGY,
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BQ27XXX_DM_TERMINATE_VOLTAGE,
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};
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#define bq27000_dm_regs 0
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#define bq27010_dm_regs 0
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#define bq2750x_dm_regs 0
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#define bq2751x_dm_regs 0
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#define bq2752x_dm_regs 0
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#if 0 /* not yet tested */
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static struct bq27xxx_dm_reg bq27500_dm_regs[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = { 48, 10, 2, 0, 65535 },
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[BQ27XXX_DM_DESIGN_ENERGY] = { }, /* missing on chip */
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[BQ27XXX_DM_TERMINATE_VOLTAGE] = { 80, 48, 2, 1000, 32767 },
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};
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#else
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#define bq27500_dm_regs 0
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#endif
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/* todo create data memory definitions from datasheets and test on chips */
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#define bq27510g1_dm_regs 0
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#define bq27510g2_dm_regs 0
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#define bq27510g3_dm_regs 0
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#define bq27520g1_dm_regs 0
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#define bq27520g2_dm_regs 0
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#define bq27520g3_dm_regs 0
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#define bq27520g4_dm_regs 0
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#define bq27530_dm_regs 0
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#define bq27531_dm_regs 0
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#define bq27541_dm_regs 0
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#define bq27542_dm_regs 0
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#define bq27546_dm_regs 0
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#define bq27742_dm_regs 0
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#if 0 /* not yet tested */
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static struct bq27xxx_dm_reg bq27545_dm_regs[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = { 48, 23, 2, 0, 32767 },
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[BQ27XXX_DM_DESIGN_ENERGY] = { 48, 25, 2, 0, 32767 },
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[BQ27XXX_DM_TERMINATE_VOLTAGE] = { 80, 67, 2, 2800, 3700 },
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};
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#else
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#define bq27545_dm_regs 0
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#endif
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#if 0 /* not yet tested */
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static struct bq27xxx_dm_reg bq27421_dm_regs[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 10, 2, 0, 8000 },
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[BQ27XXX_DM_DESIGN_ENERGY] = { 82, 12, 2, 0, 32767 },
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[BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 16, 2, 2500, 3700 },
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};
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#else
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#define bq27421_dm_regs 0
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#endif
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static struct bq27xxx_dm_reg bq27425_dm_regs[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 12, 2, 0, 32767 },
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[BQ27XXX_DM_DESIGN_ENERGY] = { 82, 14, 2, 0, 32767 },
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[BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 18, 2, 2800, 3700 },
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};
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#if 0 /* not yet tested */
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#define bq27441_dm_regs bq27421_dm_regs
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#else
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#define bq27441_dm_regs 0
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#endif
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#if 0 /* not yet tested */
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static struct bq27xxx_dm_reg bq27621_dm_regs[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = { 82, 3, 2, 0, 8000 },
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[BQ27XXX_DM_DESIGN_ENERGY] = { 82, 5, 2, 0, 32767 },
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[BQ27XXX_DM_TERMINATE_VOLTAGE] = { 82, 9, 2, 2500, 3700 },
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};
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#else
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#define bq27621_dm_regs 0
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#endif
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#define BQ27XXX_O_ZERO 0x00000001
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#define BQ27XXX_O_OTDC 0x00000002
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#define BQ27XXX_O_UTOT 0x00000004
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#define BQ27XXX_O_CFGUP 0x00000008
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#define BQ27XXX_O_RAM 0x00000010
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#define BQ27XXX_DATA(ref, opt) { \
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#define BQ27XXX_DATA(ref, key, opt) { \
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.opts = (opt), \
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.unseal_key = key, \
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.regs = ref##_regs, \
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.dm_regs = ref##_dm_regs, \
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.props = ref##_props, \
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.props_size = ARRAY_SIZE(ref##_props) }
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static struct {
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u32 opts;
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u32 unseal_key;
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u8 *regs;
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struct bq27xxx_dm_reg *dm_regs;
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enum power_supply_property *props;
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size_t props_size;
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} bq27xxx_chip_data[] = {
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[BQ27000] = BQ27XXX_DATA(bq27000, BQ27XXX_O_ZERO),
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[BQ27010] = BQ27XXX_DATA(bq27010, BQ27XXX_O_ZERO),
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[BQ2750X] = BQ27XXX_DATA(bq2750x, BQ27XXX_O_OTDC),
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[BQ2751X] = BQ27XXX_DATA(bq2751x, BQ27XXX_O_OTDC),
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[BQ2752X] = BQ27XXX_DATA(bq2752x, BQ27XXX_O_OTDC),
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[BQ27500] = BQ27XXX_DATA(bq27500, BQ27XXX_O_OTDC),
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[BQ27510G1] = BQ27XXX_DATA(bq27510g1, BQ27XXX_O_OTDC),
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[BQ27510G2] = BQ27XXX_DATA(bq27510g2, BQ27XXX_O_OTDC),
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[BQ27510G3] = BQ27XXX_DATA(bq27510g3, BQ27XXX_O_OTDC),
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[BQ27520G1] = BQ27XXX_DATA(bq27520g1, BQ27XXX_O_OTDC),
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[BQ27520G2] = BQ27XXX_DATA(bq27520g2, BQ27XXX_O_OTDC),
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[BQ27520G3] = BQ27XXX_DATA(bq27520g3, BQ27XXX_O_OTDC),
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[BQ27520G4] = BQ27XXX_DATA(bq27520g4, BQ27XXX_O_OTDC),
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[BQ27530] = BQ27XXX_DATA(bq27530, BQ27XXX_O_UTOT),
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[BQ27531] = BQ27XXX_DATA(bq27531, BQ27XXX_O_UTOT),
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[BQ27541] = BQ27XXX_DATA(bq27541, BQ27XXX_O_OTDC),
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[BQ27542] = BQ27XXX_DATA(bq27542, BQ27XXX_O_OTDC),
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[BQ27546] = BQ27XXX_DATA(bq27546, BQ27XXX_O_OTDC),
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[BQ27742] = BQ27XXX_DATA(bq27742, BQ27XXX_O_OTDC),
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[BQ27545] = BQ27XXX_DATA(bq27545, BQ27XXX_O_OTDC),
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[BQ27421] = BQ27XXX_DATA(bq27421, BQ27XXX_O_UTOT),
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[BQ27425] = BQ27XXX_DATA(bq27425, BQ27XXX_O_UTOT),
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[BQ27441] = BQ27XXX_DATA(bq27441, BQ27XXX_O_UTOT),
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[BQ27621] = BQ27XXX_DATA(bq27621, BQ27XXX_O_UTOT),
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[BQ27000] = BQ27XXX_DATA(bq27000, 0 , BQ27XXX_O_ZERO),
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[BQ27010] = BQ27XXX_DATA(bq27010, 0 , BQ27XXX_O_ZERO),
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[BQ2750X] = BQ27XXX_DATA(bq2750x, 0 , BQ27XXX_O_OTDC),
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[BQ2751X] = BQ27XXX_DATA(bq2751x, 0 , BQ27XXX_O_OTDC),
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[BQ2752X] = BQ27XXX_DATA(bq2752x, 0 , BQ27XXX_O_OTDC),
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[BQ27500] = BQ27XXX_DATA(bq27500, 0x04143672, BQ27XXX_O_OTDC),
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[BQ27510G1] = BQ27XXX_DATA(bq27510g1, 0 , BQ27XXX_O_OTDC),
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[BQ27510G2] = BQ27XXX_DATA(bq27510g2, 0 , BQ27XXX_O_OTDC),
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[BQ27510G3] = BQ27XXX_DATA(bq27510g3, 0 , BQ27XXX_O_OTDC),
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[BQ27520G1] = BQ27XXX_DATA(bq27520g1, 0 , BQ27XXX_O_OTDC),
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[BQ27520G2] = BQ27XXX_DATA(bq27520g2, 0 , BQ27XXX_O_OTDC),
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[BQ27520G3] = BQ27XXX_DATA(bq27520g3, 0 , BQ27XXX_O_OTDC),
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[BQ27520G4] = BQ27XXX_DATA(bq27520g4, 0 , BQ27XXX_O_OTDC),
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[BQ27530] = BQ27XXX_DATA(bq27530, 0 , BQ27XXX_O_UTOT),
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[BQ27531] = BQ27XXX_DATA(bq27531, 0 , BQ27XXX_O_UTOT),
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[BQ27541] = BQ27XXX_DATA(bq27541, 0 , BQ27XXX_O_OTDC),
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[BQ27542] = BQ27XXX_DATA(bq27542, 0 , BQ27XXX_O_OTDC),
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[BQ27546] = BQ27XXX_DATA(bq27546, 0 , BQ27XXX_O_OTDC),
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[BQ27742] = BQ27XXX_DATA(bq27742, 0 , BQ27XXX_O_OTDC),
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[BQ27545] = BQ27XXX_DATA(bq27545, 0x04143672, BQ27XXX_O_OTDC),
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[BQ27421] = BQ27XXX_DATA(bq27421, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
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[BQ27425] = BQ27XXX_DATA(bq27425, 0x04143672, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP),
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[BQ27441] = BQ27XXX_DATA(bq27441, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
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[BQ27621] = BQ27XXX_DATA(bq27621, 0x80008000, BQ27XXX_O_UTOT | BQ27XXX_O_CFGUP | BQ27XXX_O_RAM),
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};
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static DEFINE_MUTEX(bq27xxx_list_lock);
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@ -834,13 +924,6 @@ static LIST_HEAD(bq27xxx_battery_devices);
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#define BQ27XXX_DM_SZ 32
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struct bq27xxx_dm_reg {
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u8 subclass_id;
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u8 offset;
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u8 bytes;
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u16 min, max;
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};
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/**
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* struct bq27xxx_dm_buf - chip data memory buffer
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* @class: data memory subclass_id
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@ -873,12 +956,6 @@ static inline u16 *bq27xxx_dm_reg_ptr(struct bq27xxx_dm_buf *buf,
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return NULL;
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}
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enum bq27xxx_dm_reg_id {
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BQ27XXX_DM_DESIGN_CAPACITY = 0,
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BQ27XXX_DM_DESIGN_ENERGY,
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BQ27XXX_DM_TERMINATE_VOLTAGE,
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};
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static const char * const bq27xxx_dm_reg_name[] = {
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[BQ27XXX_DM_DESIGN_CAPACITY] = "design-capacity",
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[BQ27XXX_DM_DESIGN_ENERGY] = "design-energy",
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@ -1121,9 +1198,9 @@ static void bq27xxx_battery_update_dm_block(struct bq27xxx_device_info *di,
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}
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#ifdef CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM
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if (!di->ram_chip && !bq27xxx_dt_to_nvm) {
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if (!(di->opts & BQ27XXX_O_RAM) && !bq27xxx_dt_to_nvm) {
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#else
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if (!di->ram_chip) {
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if (!(di->opts & BQ27XXX_O_RAM)) {
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#endif
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/* devicetree and NVM differ; defer to NVM */
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dev_warn(di->dev, "%s has %u; update to %u disallowed "
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@ -1159,7 +1236,7 @@ static int bq27xxx_battery_cfgupdate_priv(struct bq27xxx_device_info *di, bool a
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return ret;
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} while (!!(ret & BQ27XXX_FLAG_CFGUP) != active && --try);
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if (!try) {
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if (!try && di->chip != BQ27425) { // 425 has a bug
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dev_err(di->dev, "timed out waiting for cfgupdate flag %d\n", active);
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return -EINVAL;
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}
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@ -1191,7 +1268,7 @@ static inline int bq27xxx_battery_soft_reset(struct bq27xxx_device_info *di)
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static int bq27xxx_battery_write_dm_block(struct bq27xxx_device_info *di,
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struct bq27xxx_dm_buf *buf)
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{
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bool cfgup = di->chip == BQ27421; /* assume related chips need cfgupdate */
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bool cfgup = di->opts & BQ27XXX_O_CFGUP;
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int ret;
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if (!buf->dirty)
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@ -1290,7 +1367,7 @@ static void bq27xxx_battery_set_config(struct bq27xxx_device_info *di,
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bq27xxx_battery_seal(di);
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if (updated && di->chip != BQ27421) { /* not a cfgupdate chip, so reset */
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if (updated && !(di->opts & BQ27XXX_O_CFGUP)) {
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bq27xxx_write(di, BQ27XXX_REG_CTRL, BQ27XXX_RESET, false);
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BQ27XXX_MSLEEP(300); /* reset time is not documented */
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}
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@ -1900,8 +1977,10 @@ int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
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INIT_DELAYED_WORK(&di->work, bq27xxx_battery_poll);
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mutex_init(&di->lock);
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di->regs = bq27xxx_chip_data[di->chip].regs;
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di->opts = bq27xxx_chip_data[di->chip].opts;
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di->regs = bq27xxx_chip_data[di->chip].regs;
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di->unseal_key = bq27xxx_chip_data[di->chip].unseal_key;
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di->dm_regs = bq27xxx_chip_data[di->chip].dm_regs;
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di->opts = bq27xxx_chip_data[di->chip].opts;
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psy_desc = devm_kzalloc(di->dev, sizeof(*psy_desc), GFP_KERNEL);
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if (!psy_desc)
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@ -1920,8 +1999,6 @@ int bq27xxx_battery_setup(struct bq27xxx_device_info *di)
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return PTR_ERR(di->bat);
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}
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dev_info(di->dev, "support ver. %s enabled\n", DRIVER_VERSION);
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bq27xxx_battery_settings(di);
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bq27xxx_battery_update(di);
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@ -54,7 +54,6 @@ struct bq27xxx_device_info {
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struct device *dev;
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int id;
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enum bq27xxx_chip chip;
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bool ram_chip;
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u32 opts;
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const char *name;
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struct bq27xxx_dm_reg *dm_regs;
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