[ARM] pxa: introduce reset_status and clear_reset_status for driver's usage
Due to the problem of reset status bits being handled by different registers between pxa2xx and pxa3xx, introduce a global reset_status variable, initialized by SoC-specific code and later being used by other drivers. And also introduce clear_reset_status(), which is used to clear the corresponding status bits. Pass RESET_STATUS_ALL to clear all bits. Signed-off-by: Eric Miao <eric.miao@marvell.com>
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@ -26,9 +26,19 @@
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#include <asm/mach/map.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/reset.h>
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#include "generic.h"
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void clear_reset_status(unsigned int mask)
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{
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if (cpu_is_pxa2xx())
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pxa2xx_clear_reset_status(mask);
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if (cpu_is_pxa3xx())
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pxa3xx_clear_reset_status(mask);
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}
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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@ -47,12 +47,20 @@ extern unsigned pxa27x_get_memclk_frequency_10khz(void);
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#define pxa27x_get_memclk_frequency_10khz() (0)
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#endif
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#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
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extern void pxa2xx_clear_reset_status(unsigned int);
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#else
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static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
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#endif
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#ifdef CONFIG_PXA3xx
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extern unsigned pxa3xx_get_clk_frequency_khz(int);
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extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
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extern void pxa3xx_clear_reset_status(unsigned int);
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#else
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#define pxa3xx_get_clk_frequency_khz(x) (0)
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#define pxa3xx_get_memclk_frequency_10khz() (0)
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static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
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#endif
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extern struct sysdev_class pxa_irq_sysclass;
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@ -28,6 +28,7 @@
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-regs.h>
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#include <asm/arch/mfp-pxa25x.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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@ -348,6 +349,9 @@ static int __init pxa25x_init(void)
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clks_register(&pxa25x_hwuart_clk, 1);
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if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
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reset_status = RCSR;
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clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
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if ((ret = pxa_init_dma(16)))
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@ -24,6 +24,7 @@
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-regs.h>
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#include <asm/arch/mfp-pxa27x.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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@ -384,6 +385,9 @@ static int __init pxa27x_init(void)
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int i, ret = 0;
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if (cpu_is_pxa27x()) {
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reset_status = RCSR;
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clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
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if ((ret = pxa_init_dma(32)))
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@ -14,10 +14,19 @@
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa2xx-regs.h>
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#include <asm/arch/mfp-pxa2xx.h>
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#include <asm/arch/mfp-pxa25x.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/irda.h>
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void pxa2xx_clear_reset_status(unsigned int mask)
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{
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/* RESET_STATUS_* has a 1:1 mapping with RCSR */
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RCSR = mask;
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}
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static unsigned long pxa2xx_mfp_fir[] = {
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GPIO46_FICP_RXD,
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GPIO47_FICP_TXD,
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@ -24,6 +24,7 @@
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#include <asm/hardware.h>
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#include <asm/arch/pxa3xx-regs.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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@ -109,6 +110,12 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
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return (clk / 10000);
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}
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void pxa3xx_clear_reset_status(unsigned int mask)
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{
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/* RESET_STATUS_* has a 1:1 mapping with ARSR */
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ARSR = mask;
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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@ -532,6 +539,9 @@ static int __init pxa3xx_init(void)
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int i, ret = 0;
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if (cpu_is_pxa3xx()) {
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reset_status = ARSR;
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/*
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* clear RDH bit every time after reset
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*
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@ -11,9 +11,11 @@
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#include <asm/proc-fns.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-regs.h>
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#include <asm/arch/reset.h>
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unsigned int reset_status;
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EXPORT_SYMBOL(reset_status);
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static void do_hw_reset(void);
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static int reset_gpio = -1;
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@ -78,8 +80,7 @@ static void do_hw_reset(void)
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void arch_reset(char mode)
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{
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if (cpu_is_pxa2xx())
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RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
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clear_reset_status(RESET_STATUS_ALL);
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switch (mode) {
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case 's':
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@ -31,6 +31,9 @@
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#include "generic.h"
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unsigned int reset_status;
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EXPORT_SYMBOL(reset_status);
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#define NR_FREQS 16
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/*
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@ -1,6 +1,15 @@
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#ifndef __ASM_ARCH_RESET_H
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#define __ASM_ARCH_RESET_H
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#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
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#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
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#define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */
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#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
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#define RESET_STATUS_ALL (0xf)
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extern unsigned int reset_status;
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extern void clear_reset_status(unsigned int mask);
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/*
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* register GPIO as reset generator
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*/
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@ -0,0 +1,18 @@
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#ifndef __ASM_ARCH_RESET_H
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#define __ASM_ARCH_RESET_H
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#include "hardware.h"
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#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
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#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
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#define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */
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#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
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#define RESET_STATUS_ALL (0xf)
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extern unsigned int reset_status;
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static inline void clear_reset_status(unsigned int mask)
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{
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RCSR = mask;
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}
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#endif /* __ASM_ARCH_RESET_H */
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