ARC: Reduce bitops lines of code using macros
No semantical changes ! Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
b8a0330239
commit
04e2eee4b0
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@ -18,83 +18,50 @@
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#include <linux/types.h>
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <linux/compiler.h>
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#include <asm/barrier.h>
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#include <asm/barrier.h>
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#ifndef CONFIG_ARC_HAS_LLSC
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#include <asm/smp.h>
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#endif
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/*
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* Hardware assisted read-modify-write using ARC700 LLOCK/SCOND insns.
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* The Kconfig glue ensures that in SMP, this is only set if the container
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* SoC/platform has cross-core coherent LLOCK/SCOND
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*/
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#if defined(CONFIG_ARC_HAS_LLSC)
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#if defined(CONFIG_ARC_HAS_LLSC)
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static inline void set_bit(unsigned long nr, volatile unsigned long *m)
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/*
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{
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* Hardware assisted Atomic-R-M-W
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unsigned int temp;
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*/
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m += nr >> 5;
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#define BIT_OP(op, c_op, asm_op) \
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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/*
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{ \
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* ARC ISA micro-optimization:
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unsigned int temp; \
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*
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\
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* Instructions dealing with bitpos only consider lower 5 bits (0-31)
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m += nr >> 5; \
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* e.g (x << 33) is handled like (x << 1) by ASL instruction
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\
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* (mem pointer still needs adjustment to point to next word)
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/* \
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*
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* ARC ISA micro-optimization: \
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* Hence the masking to clamp @nr arg can be elided in general.
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* \
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*
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* Instructions dealing with bitpos only consider lower 5 bits \
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* However if @nr is a constant (above assumed it in a register),
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* e.g (x << 33) is handled like (x << 1) by ASL instruction \
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* and greater than 31, gcc can optimize away (x << 33) to 0,
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* (mem pointer still needs adjustment to point to next word) \
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* as overflow, given the 32-bit ISA. Thus masking needs to be done
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* \
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* for constant @nr, but no code is generated due to const prop.
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* Hence the masking to clamp @nr arg can be elided in general. \
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*/
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* \
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if (__builtin_constant_p(nr))
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* However if @nr is a constant (above assumed in a register), \
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nr &= 0x1f;
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* and greater than 31, gcc can optimize away (x << 33) to 0, \
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* as overflow, given the 32-bit ISA. Thus masking needs to be \
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__asm__ __volatile__(
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* done for const @nr, but no code is generated due to gcc \
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"1: llock %0, [%1] \n"
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* const prop. \
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" bset %0, %0, %2 \n"
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*/ \
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" scond %0, [%1] \n"
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if (__builtin_constant_p(nr)) \
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" bnz 1b \n"
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nr &= 0x1f; \
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: "=&r"(temp)
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\
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: "r"(m), "ir"(nr)
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__asm__ __volatile__( \
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: "cc");
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"1: llock %0, [%1] \n" \
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}
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
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" bnz 1b \n" \
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{
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
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unsigned int temp;
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: "r"(m), /* Not "m": llock only supports reg direct addr mode */ \
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"ir"(nr) \
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m += nr >> 5;
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: "cc"); \
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bclr %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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}
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static inline void change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" bxor %0, %0, %2 \n"
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" scond %0, [%1] \n"
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" bnz 1b \n"
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: "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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}
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}
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/*
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/*
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@ -108,91 +75,38 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *m)
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* Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
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* Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
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* and the old value of bit is returned
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* and the old value of bit is returned
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*/
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*/
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static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
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#define TEST_N_BIT_OP(op, c_op, asm_op) \
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{
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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unsigned long old, temp;
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{ \
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unsigned long old, temp; \
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m += nr >> 5;
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\
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m += nr >> 5; \
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if (__builtin_constant_p(nr))
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\
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nr &= 0x1f;
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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/*
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\
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* Explicit full memory barrier needed before/after as
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/* \
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* LLOCK/SCOND themselves don't provide any such semantics
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* Explicit full memory barrier needed before/after as \
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*/
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* LLOCK/SCOND themselves don't provide any such smenatic \
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smp_mb();
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*/ \
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smp_mb(); \
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__asm__ __volatile__(
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\
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"1: llock %0, [%2] \n"
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__asm__ __volatile__( \
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" bset %1, %0, %3 \n"
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"1: llock %0, [%2] \n" \
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" scond %1, [%2] \n"
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" " #asm_op " %1, %0, %3 \n" \
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" bnz 1b \n"
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" scond %1, [%2] \n" \
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: "=&r"(old), "=&r"(temp)
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" bnz 1b \n" \
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: "r"(m), "ir"(nr)
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: "=&r"(old), "=&r"(temp) \
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: "cc");
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: "r"(m), "ir"(nr) \
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: "cc"); \
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smp_mb();
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\
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smp_mb(); \
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return (old & (1 << nr)) != 0;
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\
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}
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return (old & (1 << nr)) != 0; \
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static inline int
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test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int old, temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %0, [%2] \n"
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" bclr %1, %0, %3 \n"
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" scond %1, [%2] \n"
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" bnz 1b \n"
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: "=&r"(old), "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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smp_mb();
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return (old & (1 << nr)) != 0;
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}
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static inline int
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test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned int old, temp;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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smp_mb();
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__asm__ __volatile__(
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"1: llock %0, [%2] \n"
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" bxor %1, %0, %3 \n"
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" scond %1, [%2] \n"
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" bnz 1b \n"
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: "=&r"(old), "=&r"(temp)
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: "r"(m), "ir"(nr)
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: "cc");
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smp_mb();
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return (old & (1 << nr)) != 0;
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}
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#else /* !CONFIG_ARC_HAS_LLSC */
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#include <asm/smp.h>
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/*
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/*
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* Non hardware assisted Atomic-R-M-W
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* Non hardware assisted Atomic-R-M-W
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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@ -209,111 +123,43 @@ test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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* at compile time)
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* at compile time)
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*/
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*/
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static inline void set_bit(unsigned long nr, volatile unsigned long *m)
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#define BIT_OP(op, c_op, asm_op) \
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{
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
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unsigned long temp, flags;
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{ \
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m += nr >> 5;
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unsigned long temp, flags; \
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m += nr >> 5; \
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if (__builtin_constant_p(nr))
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\
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nr &= 0x1f;
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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bitops_lock(flags);
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\
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/* \
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temp = *m;
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* spin lock/unlock provide the needed smp_mb() before/after \
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*m = temp | (1UL << nr);
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*/ \
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bitops_lock(flags); \
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bitops_unlock(flags);
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\
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temp = *m; \
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*m = temp c_op (1UL << nr); \
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\
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bitops_unlock(flags); \
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}
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}
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static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
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#define TEST_N_BIT_OP(op, c_op, asm_op) \
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{
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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unsigned long temp, flags;
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{ \
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m += nr >> 5;
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unsigned long old, flags; \
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m += nr >> 5; \
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if (__builtin_constant_p(nr))
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\
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nr &= 0x1f;
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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bitops_lock(flags);
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\
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bitops_lock(flags); \
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temp = *m;
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\
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*m = temp & ~(1UL << nr);
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old = *m; \
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*m = old c_op (1 << nr); \
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bitops_unlock(flags);
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\
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}
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bitops_unlock(flags); \
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\
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static inline void change_bit(unsigned long nr, volatile unsigned long *m)
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return (old & (1 << nr)) != 0; \
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{
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unsigned long temp, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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temp = *m;
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*m = temp ^ (1UL << nr);
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bitops_unlock(flags);
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}
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static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long old, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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/*
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* spin lock/unlock provide the needed smp_mb() before/after
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*/
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bitops_lock(flags);
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old = *m;
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*m = old | (1 << nr);
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bitops_unlock(flags);
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return (old & (1 << nr)) != 0;
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}
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static inline int
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test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long old, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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old = *m;
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*m = old & ~(1 << nr);
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bitops_unlock(flags);
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return (old & (1 << nr)) != 0;
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}
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static inline int
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test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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{
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unsigned long old, flags;
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m += nr >> 5;
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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bitops_lock(flags);
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old = *m;
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*m = old ^ (1 << nr);
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bitops_unlock(flags);
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return (old & (1 << nr)) != 0;
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}
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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#endif /* CONFIG_ARC_HAS_LLSC */
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@ -322,86 +168,51 @@ test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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* Non atomic variants
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* Non atomic variants
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**************************************/
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**************************************/
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static inline void __set_bit(unsigned long nr, volatile unsigned long *m)
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#define __BIT_OP(op, c_op, asm_op) \
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{
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static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
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unsigned long temp;
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{ \
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m += nr >> 5;
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unsigned long temp; \
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m += nr >> 5; \
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if (__builtin_constant_p(nr))
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\
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nr &= 0x1f;
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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temp = *m;
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\
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*m = temp | (1UL << nr);
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temp = *m; \
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*m = temp c_op (1UL << nr); \
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}
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}
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static inline void __clear_bit(unsigned long nr, volatile unsigned long *m)
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#define __TEST_N_BIT_OP(op, c_op, asm_op) \
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{
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static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
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unsigned long temp;
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{ \
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m += nr >> 5;
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unsigned long old; \
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m += nr >> 5; \
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if (__builtin_constant_p(nr))
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\
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nr &= 0x1f;
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if (__builtin_constant_p(nr)) \
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nr &= 0x1f; \
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temp = *m;
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\
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*m = temp & ~(1UL << nr);
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old = *m; \
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*m = old c_op (1 << nr); \
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\
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return (old & (1 << nr)) != 0; \
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}
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}
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static inline void __change_bit(unsigned long nr, volatile unsigned long *m)
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#define BIT_OPS(op, c_op, asm_op) \
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{
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\
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unsigned long temp;
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/* set_bit(), clear_bit(), change_bit() */ \
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m += nr >> 5;
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BIT_OP(op, c_op, asm_op) \
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\
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/* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\
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TEST_N_BIT_OP(op, c_op, asm_op) \
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\
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/* __set_bit(), __clear_bit(), __change_bit() */ \
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__BIT_OP(op, c_op, asm_op) \
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\
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/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
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__TEST_N_BIT_OP(op, c_op, asm_op)
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if (__builtin_constant_p(nr))
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BIT_OPS(set, |, bset)
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nr &= 0x1f;
|
BIT_OPS(clear, & ~, bclr)
|
||||||
|
BIT_OPS(change, ^, bxor)
|
||||||
temp = *m;
|
|
||||||
*m = temp ^ (1UL << nr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int
|
|
||||||
__test_and_set_bit(unsigned long nr, volatile unsigned long *m)
|
|
||||||
{
|
|
||||||
unsigned long old;
|
|
||||||
m += nr >> 5;
|
|
||||||
|
|
||||||
if (__builtin_constant_p(nr))
|
|
||||||
nr &= 0x1f;
|
|
||||||
|
|
||||||
old = *m;
|
|
||||||
*m = old | (1 << nr);
|
|
||||||
|
|
||||||
return (old & (1 << nr)) != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int
|
|
||||||
__test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
|
|
||||||
{
|
|
||||||
unsigned long old;
|
|
||||||
m += nr >> 5;
|
|
||||||
|
|
||||||
if (__builtin_constant_p(nr))
|
|
||||||
nr &= 0x1f;
|
|
||||||
|
|
||||||
old = *m;
|
|
||||||
*m = old & ~(1 << nr);
|
|
||||||
|
|
||||||
return (old & (1 << nr)) != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int
|
|
||||||
__test_and_change_bit(unsigned long nr, volatile unsigned long *m)
|
|
||||||
{
|
|
||||||
unsigned long old;
|
|
||||||
m += nr >> 5;
|
|
||||||
|
|
||||||
if (__builtin_constant_p(nr))
|
|
||||||
nr &= 0x1f;
|
|
||||||
|
|
||||||
old = *m;
|
|
||||||
*m = old ^ (1 << nr);
|
|
||||||
|
|
||||||
return (old & (1 << nr)) != 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This routine doesn't need to be atomic.
|
* This routine doesn't need to be atomic.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue