USB: OTG: msm: Add PHY suspend support for MSM8960
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -163,6 +163,32 @@ put_3p3:
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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#define USB_PHY_SUSP_DIG_VOL 500000
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static int msm_hsusb_config_vddcx(int high)
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{
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int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
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int min_vol;
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int ret;
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if (high)
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min_vol = USB_PHY_VDD_DIG_VOL_MIN;
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else
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min_vol = USB_PHY_SUSP_DIG_VOL;
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ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
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if (ret) {
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pr_err("%s: unable to set the voltage for regulator "
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"HSUSB_VDDCX\n", __func__);
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return ret;
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}
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pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
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return ret;
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}
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#endif
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static int msm_hsusb_ldo_set_mode(int on)
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{
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int ret = 0;
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@ -434,27 +460,28 @@ static int msm_otg_suspend(struct msm_otg *motg)
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disable_irq(motg->irq);
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/*
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* Chipidea 45-nm PHY suspend sequence:
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*
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* Interrupt Latch Register auto-clear feature is not present
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* in all PHY versions. Latch register is clear on read type.
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* Clear latch register to avoid spurious wakeup from
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* low power mode (LPM).
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*/
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ulpi_read(otg, 0x14);
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/*
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*
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* PHY comparators are disabled when PHY enters into low power
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* mode (LPM). Keep PHY comparators ON in LPM only when we expect
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* VBUS/Id notifications from USB PHY. Otherwise turn off USB
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* PHY comparators. This save significant amount of power.
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*/
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if (pdata->otg_control == OTG_PHY_CONTROL)
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ulpi_write(otg, 0x01, 0x30);
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/*
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*
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* PLL is not turned off when PHY enters into low power mode (LPM).
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* Disable PLL for maximum power savings.
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*/
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ulpi_write(otg, 0x08, 0x09);
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if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
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ulpi_read(otg, 0x14);
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if (pdata->otg_control == OTG_PHY_CONTROL)
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ulpi_write(otg, 0x01, 0x30);
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ulpi_write(otg, 0x08, 0x09);
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}
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/*
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* PHY may take some time or even fail to enter into low power
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@ -485,6 +512,10 @@ static int msm_otg_suspend(struct msm_otg *motg)
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*/
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writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
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if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
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motg->pdata->otg_control == OTG_PMIC_CONTROL)
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writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
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clk_disable(motg->pclk);
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clk_disable(motg->clk);
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if (motg->core_clk)
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@ -493,6 +524,12 @@ static int msm_otg_suspend(struct msm_otg *motg)
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if (!IS_ERR(motg->pclk_src))
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clk_disable(motg->pclk_src);
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if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
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motg->pdata->otg_control == OTG_PMIC_CONTROL) {
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msm_hsusb_ldo_set_mode(0);
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msm_hsusb_config_vddcx(0);
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}
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if (device_may_wakeup(otg->dev))
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enable_irq_wake(motg->irq);
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if (bus)
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@ -524,6 +561,13 @@ static int msm_otg_resume(struct msm_otg *motg)
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if (motg->core_clk)
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clk_enable(motg->core_clk);
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if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
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motg->pdata->otg_control == OTG_PMIC_CONTROL) {
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msm_hsusb_ldo_set_mode(1);
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msm_hsusb_config_vddcx(1);
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writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
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}
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temp = readl(USB_USBCMD);
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temp &= ~ASYNC_INTR_CTRL;
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temp &= ~ULPI_STP_CTRL;
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@ -24,6 +24,7 @@
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#define USB_PORTSC (MSM_USB_BASE + 0x0184)
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#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
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#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
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#define USB_PHY_CTRL (MSM_USB_BASE + 0x0240)
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#define USBCMD_RESET 2
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#define USB_USBINTR (MSM_USB_BASE + 0x0148)
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@ -42,6 +43,7 @@
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#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */
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#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */
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#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */
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/* OTG definitions */
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#define OTGSC_INTSTS_MASK (0x7f << 16)
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