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drm/amdgpu/gfx8: fix priv reg interrupt enable 

Looks like a copy/paste typo.

Reviewed-by: Christian König <christian.koenig@amd.com>
Noticed-by: David Panariti <David.Panariti@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-02-18 11:10:09 -05:00
parent e1d09dc0cc
commit 04ab3b7622
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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@ -4995,7 +4995,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
case AMDGPU_IRQ_STATE_ENABLE:
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
PRIV_REG_INT_ENABLE, 0);
PRIV_REG_INT_ENABLE, 1);
WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
break;
default: