Renesas RZ/V2M DT Binding Definitions
Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYnOhkgAKCRCKwlD9ZEnx cCbbAQCUh1AapeMlmEvhNIPN7NH5tE6EdpHJcTRrHXOhU1uT5QD/RLavj37xoyU0 W519FwTA0oYGsXCq2yXjQ08DwlrkUg0= =nWXL -----END PGP SIGNATURE----- Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19 Renesas RZ/V2M DT Binding Definitions Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by driver and DT source files.
This commit is contained in:
Geert Uytterhoeven
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049bddcb89
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
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#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* Module Clocks */
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#define R9A09G011_SYS_CLK 0
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#define R9A09G011_PFC_PCLK 1
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#define R9A09G011_PMC_CORE_CLOCK 2
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#define R9A09G011_GIC_CLK 3
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#define R9A09G011_RAMA_ACLK 4
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#define R9A09G011_ROMA_ACLK 5
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#define R9A09G011_SEC_ACLK 6
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#define R9A09G011_SEC_PCLK 7
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#define R9A09G011_SEC_TCLK 8
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#define R9A09G011_DMAA_ACLK 9
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#define R9A09G011_TSU0_PCLK 10
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#define R9A09G011_TSU1_PCLK 11
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#define R9A09G011_CST_TRACECLK 12
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#define R9A09G011_CST_SB_CLK 13
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#define R9A09G011_CST_AHB_CLK 14
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#define R9A09G011_CST_ATB_SB_CLK 15
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#define R9A09G011_CST_TS_SB_CLK 16
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#define R9A09G011_SDI0_ACLK 17
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#define R9A09G011_SDI0_IMCLK 18
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#define R9A09G011_SDI0_IMCLK2 19
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#define R9A09G011_SDI0_CLK_HS 20
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#define R9A09G011_SDI1_ACLK 21
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#define R9A09G011_SDI1_IMCLK 22
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#define R9A09G011_SDI1_IMCLK2 23
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#define R9A09G011_SDI1_CLK_HS 24
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#define R9A09G011_EMM_ACLK 25
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#define R9A09G011_EMM_IMCLK 26
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#define R9A09G011_EMM_IMCLK2 27
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#define R9A09G011_EMM_CLK_HS 28
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#define R9A09G011_NFI_ACLK 29
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#define R9A09G011_NFI_NF_CLK 30
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#define R9A09G011_PCI_ACLK 31
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#define R9A09G011_PCI_CLK_PMU 32
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#define R9A09G011_PCI_APB_CLK 33
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#define R9A09G011_USB_ACLK_H 34
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#define R9A09G011_USB_ACLK_P 35
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#define R9A09G011_USB_PCLK 36
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#define R9A09G011_ETH0_CLK_AXI 37
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#define R9A09G011_ETH0_CLK_CHI 38
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#define R9A09G011_ETH0_GPTP_EXT 39
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#define R9A09G011_SDT_CLK 40
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#define R9A09G011_SDT_CLKAPB 41
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#define R9A09G011_SDT_CLK48 42
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#define R9A09G011_GRP_CLK 43
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#define R9A09G011_CIF_P0_CLK 44
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#define R9A09G011_CIF_P1_CLK 45
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#define R9A09G011_CIF_APB_CLK 46
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#define R9A09G011_DCI_CLKAXI 47
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#define R9A09G011_DCI_CLKAPB 48
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#define R9A09G011_DCI_CLKDCI2 49
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#define R9A09G011_HMI_PCLK 50
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#define R9A09G011_LCI_PCLK 51
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#define R9A09G011_LCI_ACLK 52
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#define R9A09G011_LCI_VCLK 53
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#define R9A09G011_LCI_LPCLK 54
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#define R9A09G011_AUI_CLK 55
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#define R9A09G011_AUI_CLKAXI 56
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#define R9A09G011_AUI_CLKAPB 57
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#define R9A09G011_AUMCLK 58
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#define R9A09G011_GMCLK0 59
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#define R9A09G011_GMCLK1 60
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#define R9A09G011_MTR_CLK0 61
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#define R9A09G011_MTR_CLK1 62
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#define R9A09G011_MTR_CLKAPB 63
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#define R9A09G011_GFT_CLK 64
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#define R9A09G011_GFT_CLKAPB 65
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#define R9A09G011_GFT_MCLK 66
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#define R9A09G011_ATGA_CLK 67
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#define R9A09G011_ATGA_CLKAPB 68
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#define R9A09G011_ATGB_CLK 69
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#define R9A09G011_ATGB_CLKAPB 70
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#define R9A09G011_SYC_CNT_CLK 71
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#define R9A09G011_CPERI_GRPA_PCLK 72
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#define R9A09G011_TIM0_CLK 73
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#define R9A09G011_TIM1_CLK 74
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#define R9A09G011_TIM2_CLK 75
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#define R9A09G011_TIM3_CLK 76
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#define R9A09G011_TIM4_CLK 77
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#define R9A09G011_TIM5_CLK 78
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#define R9A09G011_TIM6_CLK 79
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#define R9A09G011_TIM7_CLK 80
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#define R9A09G011_IIC_PCLK0 81
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#define R9A09G011_CPERI_GRPB_PCLK 82
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#define R9A09G011_TIM8_CLK 83
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#define R9A09G011_TIM9_CLK 84
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#define R9A09G011_TIM10_CLK 85
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#define R9A09G011_TIM11_CLK 86
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#define R9A09G011_TIM12_CLK 87
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#define R9A09G011_TIM13_CLK 88
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#define R9A09G011_TIM14_CLK 89
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#define R9A09G011_TIM15_CLK 90
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#define R9A09G011_IIC_PCLK1 91
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#define R9A09G011_CPERI_GRPC_PCLK 92
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#define R9A09G011_TIM16_CLK 93
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#define R9A09G011_TIM17_CLK 94
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#define R9A09G011_TIM18_CLK 95
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#define R9A09G011_TIM19_CLK 96
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#define R9A09G011_TIM20_CLK 97
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#define R9A09G011_TIM21_CLK 98
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#define R9A09G011_TIM22_CLK 99
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#define R9A09G011_TIM23_CLK 100
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#define R9A09G011_WDT0_PCLK 101
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#define R9A09G011_WDT0_CLK 102
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#define R9A09G011_WDT1_PCLK 103
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#define R9A09G011_WDT1_CLK 104
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#define R9A09G011_CPERI_GRPD_PCLK 105
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#define R9A09G011_TIM24_CLK 106
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#define R9A09G011_TIM25_CLK 107
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#define R9A09G011_TIM26_CLK 108
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#define R9A09G011_TIM27_CLK 109
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#define R9A09G011_TIM28_CLK 110
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#define R9A09G011_TIM29_CLK 111
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#define R9A09G011_TIM30_CLK 112
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#define R9A09G011_TIM31_CLK 113
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#define R9A09G011_CPERI_GRPE_PCLK 114
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#define R9A09G011_PWM0_CLK 115
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#define R9A09G011_PWM1_CLK 116
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#define R9A09G011_PWM2_CLK 117
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#define R9A09G011_PWM3_CLK 118
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#define R9A09G011_PWM4_CLK 119
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#define R9A09G011_PWM5_CLK 120
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#define R9A09G011_PWM6_CLK 121
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#define R9A09G011_PWM7_CLK 122
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#define R9A09G011_CPERI_GRPF_PCLK 123
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#define R9A09G011_PWM8_CLK 124
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#define R9A09G011_PWM9_CLK 125
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#define R9A09G011_PWM10_CLK 126
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#define R9A09G011_PWM11_CLK 127
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#define R9A09G011_PWM12_CLK 128
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#define R9A09G011_PWM13_CLK 129
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#define R9A09G011_PWM14_CLK 130
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#define R9A09G011_PWM15_CLK 131
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#define R9A09G011_CPERI_GRPG_PCLK 132
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#define R9A09G011_CPERI_GRPH_PCLK 133
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#define R9A09G011_URT_PCLK 134
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#define R9A09G011_URT0_CLK 135
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#define R9A09G011_URT1_CLK 136
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#define R9A09G011_CSI0_CLK 137
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#define R9A09G011_CSI1_CLK 138
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#define R9A09G011_CSI2_CLK 139
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#define R9A09G011_CSI3_CLK 140
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#define R9A09G011_CSI4_CLK 141
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#define R9A09G011_CSI5_CLK 142
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#define R9A09G011_ICB_ACLK1 143
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#define R9A09G011_ICB_GIC_CLK 144
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#define R9A09G011_ICB_MPCLK1 145
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#define R9A09G011_ICB_SPCLK1 146
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#define R9A09G011_ICB_CLK48 147
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#define R9A09G011_ICB_CLK48_2 148
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#define R9A09G011_ICB_CLK48_3 149
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#define R9A09G011_ICB_CLK48_4L 150
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#define R9A09G011_ICB_CLK48_4R 151
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#define R9A09G011_ICB_CLK48_5 152
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#define R9A09G011_ICB_CST_ATB_SB_CLK 153
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#define R9A09G011_ICB_CST_CS_CLK 154
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#define R9A09G011_ICB_CLK100_1 155
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#define R9A09G011_ICB_ETH0_CLK_AXI 156
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#define R9A09G011_ICB_DCI_CLKAXI 157
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#define R9A09G011_ICB_SYC_CNT_CLK 158
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#define R9A09G011_ICB_DRPA_ACLK 159
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#define R9A09G011_ICB_RFX_ACLK 160
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#define R9A09G011_ICB_RFX_PCLK5 161
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#define R9A09G011_ICB_MMC_ACLK 162
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#define R9A09G011_ICB_MPCLK3 163
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#define R9A09G011_ICB_CIMA_CLK 164
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#define R9A09G011_ICB_CIMB_CLK 165
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#define R9A09G011_ICB_BIMA_CLK 166
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#define R9A09G011_ICB_FCD_CLKAXI 167
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#define R9A09G011_ICB_VD_ACLK4 168
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#define R9A09G011_ICB_MPCLK4 169
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#define R9A09G011_ICB_VCD_PCLK4 170
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#define R9A09G011_CA53_CLK 171
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#define R9A09G011_CA53_ACLK 172
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#define R9A09G011_CA53_APCLK_DBG 173
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#define R9A09G011_CST_APB_CA53_CLK 174
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#define R9A09G011_CA53_ATCLK 175
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#define R9A09G011_CST_CS_CLK 176
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#define R9A09G011_CA53_TSCLK 177
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#define R9A09G011_CST_TS_CLK 178
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#define R9A09G011_CA53_APCLK_REG 179
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#define R9A09G011_DRPA_ACLK 180
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#define R9A09G011_DRPA_DCLK 181
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#define R9A09G011_DRPA_INITCLK 182
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#define R9A09G011_RAMB0_ACLK 183
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#define R9A09G011_RAMB1_ACLK 184
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#define R9A09G011_RAMB2_ACLK 185
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#define R9A09G011_RAMB3_ACLK 186
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#define R9A09G011_CIMA_CLKAPB 187
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#define R9A09G011_CIMA_CLK 188
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#define R9A09G011_CIMB_CLK 189
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#define R9A09G011_FAFA_CLK 190
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#define R9A09G011_STG_CLKAXI 191
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#define R9A09G011_STG_CLK0 192
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#define R9A09G011_BIMA_CLKAPB 193
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#define R9A09G011_BIMA_CLK 194
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#define R9A09G011_FAFB_CLK 195
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#define R9A09G011_FCD_CLK 196
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#define R9A09G011_FCD_CLKAXI 197
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#define R9A09G011_RIM_CLK 198
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#define R9A09G011_VCD_ACLK 199
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#define R9A09G011_VCD_PCLK 200
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#define R9A09G011_JPG0_CLK 201
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#define R9A09G011_JPG0_ACLK 202
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#define R9A09G011_MMC_CORE_DDRC_CLK 203
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#define R9A09G011_MMC_ACLK 204
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#define R9A09G011_MMC_PCLK 205
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#define R9A09G011_DDI_APBCLK 206
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/* Resets */
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#define R9A09G011_SYS_RST_N 0
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#define R9A09G011_PFC_PRESETN 1
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#define R9A09G011_RAMA_ARESETN 2
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#define R9A09G011_ROM_ARESETN 3
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#define R9A09G011_DMAA_ARESETN 4
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#define R9A09G011_SEC_ARESETN 5
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#define R9A09G011_SEC_PRESETN 6
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#define R9A09G011_SEC_RSTB 7
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#define R9A09G011_TSU0_RESETN 8
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#define R9A09G011_TSU1_RESETN 9
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#define R9A09G011_PMC_RESET_N 10
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#define R9A09G011_CST_NTRST 11
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#define R9A09G011_CST_NPOTRST 12
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#define R9A09G011_CST_NTRST2 13
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#define R9A09G011_CST_CS_RESETN 14
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#define R9A09G011_CST_TS_RESETN 15
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#define R9A09G011_CST_TRESETN 16
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#define R9A09G011_CST_SB_RESETN 17
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#define R9A09G011_CST_AHB_RESETN 18
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#define R9A09G011_CST_TS_SB_RESETN 19
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#define R9A09G011_CST_APB_CA53_RESETN 20
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#define R9A09G011_CST_ATB_SB_RESETN 21
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#define R9A09G011_SDI0_IXRST 22
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#define R9A09G011_SDI1_IXRST 23
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#define R9A09G011_EMM_IXRST 24
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#define R9A09G011_NFI_MARESETN 25
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#define R9A09G011_NFI_REG_RST_N 26
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#define R9A09G011_USB_PRESET_N 27
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#define R9A09G011_USB_DRD_RESET 28
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#define R9A09G011_USB_ARESETN_P 29
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#define R9A09G011_USB_ARESETN_H 30
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#define R9A09G011_ETH0_RST_HW_N 31
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#define R9A09G011_PCI_ARESETN 32
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#define R9A09G011_SDT_RSTSYSAX 33
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#define R9A09G011_GRP_RESETN 34
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#define R9A09G011_CIF_RST_N 35
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#define R9A09G011_DCU_RSTSYSAX 36
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#define R9A09G011_HMI_RST_N 37
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#define R9A09G011_HMI_PRESETN 38
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#define R9A09G011_LCI_PRESETN 39
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#define R9A09G011_LCI_ARESETN 40
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#define R9A09G011_AUI_RSTSYSAX 41
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#define R9A09G011_MTR_RSTSYSAX 42
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#define R9A09G011_GFT_RSTSYSAX 43
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#define R9A09G011_ATGA_RSTSYSAX 44
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#define R9A09G011_ATGB_RSTSYSAX 45
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#define R9A09G011_SYC_RST_N 46
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#define R9A09G011_TIM_GPA_PRESETN 47
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#define R9A09G011_TIM_GPB_PRESETN 48
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#define R9A09G011_TIM_GPC_PRESETN 49
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#define R9A09G011_TIM_GPD_PRESETN 50
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#define R9A09G011_PWM_GPE_PRESETN 51
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#define R9A09G011_PWM_GPF_PRESETN 52
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#define R9A09G011_CSI_GPG_PRESETN 53
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#define R9A09G011_CSI_GPH_PRESETN 54
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#define R9A09G011_IIC_GPA_PRESETN 55
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#define R9A09G011_IIC_GPB_PRESETN 56
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#define R9A09G011_URT_PRESETN 57
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#define R9A09G011_WDT0_PRESETN 58
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#define R9A09G011_WDT1_PRESETN 59
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#define R9A09G011_ICB_PD_AWO_RST_N 60
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#define R9A09G011_ICB_PD_MMC_RST_N 61
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#define R9A09G011_ICB_PD_VD0_RST_N 62
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#define R9A09G011_ICB_PD_VD1_RST_N 63
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#define R9A09G011_ICB_PD_RFX_RST_N 64
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#define R9A09G011_CA53_NCPUPORESET0 65
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#define R9A09G011_CA53_NCPUPORESET1 66
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#define R9A09G011_CA53_NCORERESET0 67
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#define R9A09G011_CA53_NCORERESET1 68
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#define R9A09G011_CA53_NPRESETDBG 69
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#define R9A09G011_CA53_L2RESET 70
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#define R9A09G011_CA53_NMISCRESET_HM 71
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#define R9A09G011_CA53_NMISCRESET_SM 72
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#define R9A09G011_CA53_NARESET 73
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#define R9A09G011_DRPA_ARESETN 74
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#define R9A09G011_RAMB0_ARESETN 75
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#define R9A09G011_RAMB1_ARESETN 76
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#define R9A09G011_RAMB2_ARESETN 77
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#define R9A09G011_RAMB3_ARESETN 78
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#define R9A09G011_CIMA_RSTSYSAX 79
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#define R9A09G011_CIMB_RSTSYSAX 80
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#define R9A09G011_FAFA_RSTSYSAX 81
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#define R9A09G011_STG_RSTSYSAX 82
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#define R9A09G011_BIMA_RSTSYSAX 83
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#define R9A09G011_FAFB_RSTSYSAX 84
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#define R9A09G011_FCD_RSTSYSAX 85
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#define R9A09G011_RIM_RSTSYSAX 86
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#define R9A09G011_VCD_RESETN 87
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#define R9A09G011_JPG_XRESET 88
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#define R9A09G011_MMC_CORE_DDRC_RSTN 89
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#define R9A09G011_MMC_ARESETN_N 90
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#define R9A09G011_MMC_PRESETN 91
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#define R9A09G011_DDI_PWROK 92
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#define R9A09G011_DDI_RESET 93
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#define R9A09G011_DDI_RESETN_APB 94
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#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */
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Reference in New Issue