drm/i915: fix Haswell FDI link training code
This commit makes hsw_fdi_link_train responsible for implementing
everything described in the "Enable and train FDI" section from the
Hawell CRT mode set sequence documentation. We completely rewrite
hsw_fdi_link_train to match the documentation and we also call it in
the right place.
This patch was initially sent as a series of tiny patches fixing every
little problem of the function, but since there were too many patches
fixing the same function it got a little difficult to get the "big
picture" of how the function would be in the end, so here we amended
all the patches into a single big patch fixing the whole function.
Problems we fixed:
1 - Train Haswell FDI at the right time.
We need to train the FDI before enabling the pipes and planes, so
we're moving the call from lpt_pch_enable to haswell_crtc_enable
directly.
We are also removing ironlake_fdi_pll_enable since the PLL
enablement on Haswell is completely different and is also done
during the link training steps.
2 - Use the right FDI_RX_CTL register on Haswell
There is only one PCH transcoder, so it's always _FDI_RXA_CTL.
Using "pipe" here is wrong.
3 - Don't rely on DDI_BUF_CTL previous values
Just set the bits we want, everything else is zero. Also
POSTING_READ the register before sleeping.
4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train
According to the mode set sequence documentation, this is the
right place. According to the FDI_RX_TUSIZE register description,
this is the value we should set.
Also remove the code that sets this register from the old
location: lpt_pch_enable.
5 - Properly program FDI_RX_MISC pwrdn lane values on HSW
6 - Wait only 35us for the FDI link training
First we wait 30us for the FDI receiver lane calibration, then we
wait 5us for the FDI auto training time.
7 - Remove an useless indentation level on hsw_fdi_link_train
We already "break" when the link training succeeds.
8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
When we fail the training.
9 - Change Haswell FDI link training error messages
We shouldn't call DRM_ERROR when still looping through voltage
levels since this is expected and not really a failure. So in this
commit we adjust the error path to only DRM_ERROR when we really
fail after trying everything.
While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since
it's what we use everywhere.
10 - Try each voltage twice at hsw_fdi_link_train
Now with Daniel Vetter's suggestion to use "/2" instead of ">>1".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Applied tiny bikesheds:
- mention in comment that we test each voltage/emphasis level twice
- realing arguments of the only untouched reg write, it spilled over
the 80 char limit ...]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni
Daniel Vetter
parent
547dc041df
commit
049456416f
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@ -3936,16 +3936,21 @@
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#define FDI_PORT_WIDTH_2X_LPT (1<<19)
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#define FDI_PORT_WIDTH_1X_LPT (0<<19)
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#define _FDI_RXA_MISC 0xf0010
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#define _FDI_RXB_MISC 0xf1010
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#define _FDI_RXA_MISC 0xf0010
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#define _FDI_RXB_MISC 0xf1010
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#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
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#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
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#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
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#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
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#define FDI_RX_TP1_TO_TP2_48 (2<<20)
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#define FDI_RX_TP1_TO_TP2_64 (3<<20)
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#define FDI_RX_FDI_DELAY_90 (0x90<<0)
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#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
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#define _FDI_RXA_TUSIZE1 0xf0030
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#define _FDI_RXA_TUSIZE2 0xf0038
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#define _FDI_RXB_TUSIZE1 0xf1030
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#define _FDI_RXB_TUSIZE2 0xf1038
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#define FDI_RX_TP1_TO_TP2_48 (2<<20)
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#define FDI_RX_TP1_TO_TP2_64 (3<<20)
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#define FDI_RX_FDI_DELAY_90 (0x90<<0)
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#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
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#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
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#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
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@ -153,11 +153,34 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 reg, temp, i;
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u32 temp, i, rx_ctl_val;
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/* Start the training iterating through available voltages and emphasis */
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for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
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/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
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* mode set "sequence for CRT port" document:
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* - TP1 to TP2 time with the default value
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* - FDI delay to 90h
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*/
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I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
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FDI_RX_PWRDN_LANE0_VAL(2) |
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FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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/* Enable the PCH Receiver FDI PLL */
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rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 19);
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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udelay(220);
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/* Switch from Rawclk to PCDclk */
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rx_ctl_val |= FDI_PCDCLK;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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/* Configure Port Clock Select */
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I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
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/* Start the training iterating through available voltages and emphasis,
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* testing each value twice. */
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for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
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/* Configure DP_TP_CTL with auto-training */
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I915_WRITE(DP_TP_CTL(PORT_E),
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DP_TP_CTL_FDI_AUTOTRAIN |
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@ -166,65 +189,63 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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DP_TP_CTL_ENABLE);
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/* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
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temp = I915_READ(DDI_BUF_CTL(PORT_E));
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temp = (temp & ~DDI_BUF_EMP_MASK);
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I915_WRITE(DDI_BUF_CTL(PORT_E),
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temp |
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DDI_BUF_CTL_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 1) |
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hsw_ddi_buf_ctl_values[i]);
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DDI_BUF_CTL_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 1) |
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hsw_ddi_buf_ctl_values[i / 2]);
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POSTING_READ(DDI_BUF_CTL(PORT_E));
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udelay(600);
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/* We need to program FDI_RX_MISC with the default TP1 to TP2
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* values before enabling the receiver, and configure the delay
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* for the FDI timing generator to 90h. Luckily, all the other
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* bits are supposed to be zeroed, so we can write those values
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* directly.
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*/
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I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 |
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FDI_RX_FDI_DELAY_90);
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/* Program PCH FDI Receiver TU */
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I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
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/* Enable CPU FDI Receiver with auto-training */
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reg = FDI_RX_CTL(pipe);
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I915_WRITE(reg,
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I915_READ(reg) |
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FDI_LINK_TRAIN_AUTO |
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FDI_RX_ENABLE |
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FDI_LINK_TRAIN_PATTERN_1_CPT |
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FDI_RX_ENHANCE_FRAME_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 19) |
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FDI_RX_PLL_ENABLE);
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POSTING_READ(reg);
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udelay(100);
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/* Enable PCH FDI Receiver with auto-training */
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rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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/* Wait for FDI receiver lane calibration */
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udelay(30);
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/* Unset FDI_RX_MISC pwrdn lanes */
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temp = I915_READ(_FDI_RXA_MISC);
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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I915_WRITE(_FDI_RXA_MISC, temp);
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POSTING_READ(_FDI_RXA_MISC);
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/* Wait for FDI auto training time */
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udelay(5);
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temp = I915_READ(DP_TP_STATUS(PORT_E));
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if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
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DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
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DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
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/* Enable normal pixel sending for FDI */
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I915_WRITE(DP_TP_CTL(PORT_E),
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DP_TP_CTL_FDI_AUTOTRAIN |
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DP_TP_CTL_LINK_TRAIN_NORMAL |
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DP_TP_CTL_ENHANCED_FRAME_ENABLE |
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DP_TP_CTL_ENABLE);
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DP_TP_CTL_FDI_AUTOTRAIN |
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DP_TP_CTL_LINK_TRAIN_NORMAL |
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DP_TP_CTL_ENHANCED_FRAME_ENABLE |
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DP_TP_CTL_ENABLE);
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break;
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} else {
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DRM_ERROR("Error training BUF_CTL %d\n", i);
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/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
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I915_WRITE(DP_TP_CTL(PORT_E),
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I915_READ(DP_TP_CTL(PORT_E)) &
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~DP_TP_CTL_ENABLE);
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I915_WRITE(FDI_RX_CTL(pipe),
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I915_READ(FDI_RX_CTL(pipe)) &
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~FDI_RX_PLL_ENABLE);
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continue;
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return;
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}
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/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
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I915_WRITE(DP_TP_CTL(PORT_E),
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I915_READ(DP_TP_CTL(PORT_E)) & ~DP_TP_CTL_ENABLE);
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rx_ctl_val &= ~FDI_RX_ENABLE;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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/* Reset FDI_RX_MISC pwrdn lanes */
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temp = I915_READ(_FDI_RXA_MISC);
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
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I915_WRITE(_FDI_RXA_MISC, temp);
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}
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DRM_DEBUG_KMS("FDI train done.\n");
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DRM_ERROR("FDI link training failed!\n");
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}
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/* WRPLL clock dividers */
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@ -3224,19 +3224,10 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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assert_transcoder_disabled(dev_priv, TRANSCODER_A);
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/* Write the TU size bits before fdi link training, so that error
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* detection works. */
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I915_WRITE(FDI_RX_TUSIZE1(pipe),
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I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
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/* For PCH output, training FDI link */
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dev_priv->display.fdi_link_train(crtc);
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lpt_program_iclkip(crtc);
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/* Set transcoder timing. */
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@ -3463,7 +3454,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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is_pch_port = haswell_crtc_driving_pch(crtc);
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if (is_pch_port)
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ironlake_fdi_pll_enable(intel_crtc);
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dev_priv->display.fdi_link_train(crtc);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_enable)
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