UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/i915: Name our BARs based on the spec 

We use all kinds of weird names for our base address registers.
Take the names from the spec and stick to them to avoid confusing
everyone.

The only exceptions are IOBAR and LMEMBAR since naming them
IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think
that adding the _BAR to GTTMMADR & co. (which don't have one
in the spec name) does make it more clear what they are.
And IOBAR vs. GTTMMADR_BAR also looks a bit too inconsistent
for my taste.

v2: Fix gvt build
v3: Add GEN2_IO_BAR for completeness

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221005195646.17201-1-ville.syrjala@linux.intel.com
Acked-by: Matthew Auld <matthew.auld@intel.com>
This commit is contained in:
Ville Syrjälä 2022-10-05 22:56:46 +03:00
parent 5bfcff516c
commit 0492a34c83
4 changed files with 27 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_lpe_audio.c
View File

@ -101,9 +101,9 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
rsc[0].flags = IORESOURCE_IRQ;
rsc[0].name = "hdmi-lpe-audio-irq";
rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) +
rsc[1].start = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) +
I915_HDMI_LPE_AUDIO_BASE;
rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) +
rsc[1].end = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) +
I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1;
rsc[1].flags = IORESOURCE_MEM;
rsc[1].name = "hdmi-lpe-audio-mmio";

12
drivers/gpu/drm/i915/gt/intel_ggtt.c
View File

@ -871,8 +871,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
u32 pte_flags;
int ret;
GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915);
GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
/*
* On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
@ -932,10 +932,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
u16 snb_gmch_ctl;
if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR))
return -ENXIO;
ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
}
@ -1089,10 +1089,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
unsigned int size;
u16 snb_gmch_ctl;
if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR))
if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR))
return -ENXIO;
ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR);
ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
/*

4
drivers/gpu/drm/i915/gvt/cfg_space.c
View File

@ -354,9 +354,9 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
pci_resource_len(pdev, GTTMMADR_BAR);
pci_resource_len(pdev, GEN4_GTTMMADR_BAR);
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
pci_resource_len(pdev, GTT_APERTURE_BAR);
pci_resource_len(pdev, GEN4_GMADR_BAR);
memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);

24
drivers/gpu/drm/i915/intel_pci_config.h
View File

@ -7,17 +7,27 @@
#define __INTEL_PCI_CONFIG_H__
/* PCI BARs */
#define GTTMMADR_BAR 0
#define GEN2_GTTMMADR_BAR 1
#define GFXMEM_BAR 2
#define GTT_APERTURE_BAR GFXMEM_BAR
#define GEN12_LMEM_BAR GFXMEM_BAR
#define GEN2_GMADR_BAR 0
#define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */
#define GEN2_IO_BAR 2 /* 85x/865 */
#define GEN3_MMADR_BAR 0 /* MMIO only */
#define GEN3_IO_BAR 1
#define GEN3_GMADR_BAR 2
#define GEN3_GTTADR_BAR 3 /* GTT only */
#define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */
#define GEN4_GMADR_BAR 2
#define GEN4_IO_BAR 4
#define GEN12_LMEM_BAR 2
static inline int intel_mmio_bar(int graphics_ver)
{
switch (graphics_ver) {
case 2: return GEN2_GTTMMADR_BAR;
default: return GTTMMADR_BAR;
case 2: return GEN2_MMADR_BAR;
case 3: return GEN3_MMADR_BAR;
default: return GEN4_GTTMMADR_BAR;
}
}