drm/amdgpu: enable VCN RAS poison for VCN v4.0
Configure related registers. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -862,6 +862,28 @@ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
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return;
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return;
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}
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}
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static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
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bool indirect)
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{
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uint32_t tmp;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
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return;
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tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
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VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
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VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
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VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
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WREG32_SOC15_DPG_MODE(inst_idx,
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SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
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tmp, 0, indirect);
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tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
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WREG32_SOC15_DPG_MODE(inst_idx,
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SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
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tmp, 0, indirect);
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}
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/**
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/**
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* vcn_v4_0_start_dpg_mode - VCN start with dpg mode
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* vcn_v4_0_start_dpg_mode - VCN start with dpg mode
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*
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*
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@ -950,6 +972,8 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
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VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
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vcn_v4_0_enable_ras(adev, inst_idx, indirect);
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/* enable master interrupt */
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/* enable master interrupt */
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, regUVD_MASTINT_EN),
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VCN, inst_idx, regUVD_MASTINT_EN),
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