serial: mps2-uart: add MPS2 UART driver
This driver adds support to the UART controller found on ARM MPS2 platform. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Vladimir Murzin
Greg Kroah-Hartman
parent
8a872e770f
commit
041f031def
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@ -1448,6 +1448,18 @@ config SERIAL_EFM32_UART
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This driver support the USART and UART ports on
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Energy Micro's efm32 SoCs.
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config SERIAL_MPS2_UART_CONSOLE
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bool "MPS2 UART console support"
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depends on SERIAL_MPS2_UART
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select SERIAL_CORE_CONSOLE
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config SERIAL_MPS2_UART
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bool "MPS2 UART port"
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depends on ARM || COMPILE_TEST
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select SERIAL_CORE
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help
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This driver support the UART ports on ARM MPS2.
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config SERIAL_EFM32_UART_CONSOLE
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bool "EFM32 UART/USART console support"
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depends on SERIAL_EFM32_UART=y
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@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
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obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
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obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
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obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o
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obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
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# GPIOLIB helpers for modem control lines
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obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
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@ -0,0 +1,597 @@
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/*
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* Copyright (C) 2015 ARM Limited
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*
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* Author: Vladimir Murzin <vladimir.murzin@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* TODO: support for SysRq
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/tty_flip.h>
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#include <linux/types.h>
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#define SERIAL_NAME "ttyMPS"
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#define DRIVER_NAME "mps2-uart"
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#define MAKE_NAME(x) (DRIVER_NAME # x)
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#define UARTn_DATA 0x00
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#define UARTn_STATE 0x04
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#define UARTn_STATE_TX_FULL BIT(0)
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#define UARTn_STATE_RX_FULL BIT(1)
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#define UARTn_STATE_TX_OVERRUN BIT(2)
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#define UARTn_STATE_RX_OVERRUN BIT(3)
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#define UARTn_CTRL 0x08
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#define UARTn_CTRL_TX_ENABLE BIT(0)
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#define UARTn_CTRL_RX_ENABLE BIT(1)
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#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
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#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
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#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
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#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
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#define UARTn_INT 0x0c
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#define UARTn_INT_TX BIT(0)
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#define UARTn_INT_RX BIT(1)
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#define UARTn_INT_TX_OVERRUN BIT(2)
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#define UARTn_INT_RX_OVERRUN BIT(3)
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#define UARTn_BAUDDIV 0x10
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#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
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/*
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* Helpers to make typical enable/disable operations more readable.
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*/
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#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
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UARTn_CTRL_TX_INT_ENABLE |\
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UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
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#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
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UARTn_CTRL_RX_INT_ENABLE |\
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UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
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#define MPS2_MAX_PORTS 3
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struct mps2_uart_port {
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struct uart_port port;
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struct clk *clk;
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unsigned int tx_irq;
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unsigned int rx_irq;
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};
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static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
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{
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return container_of(port, struct mps2_uart_port, port);
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}
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static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
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{
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struct mps2_uart_port *mps_port = to_mps2_port(port);
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writeb(val, mps_port->port.membase + off);
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}
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static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
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{
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struct mps2_uart_port *mps_port = to_mps2_port(port);
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return readb(mps_port->port.membase + off);
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}
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static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
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{
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struct mps2_uart_port *mps_port = to_mps2_port(port);
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writel_relaxed(val, mps_port->port.membase + off);
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}
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static unsigned int mps2_uart_tx_empty(struct uart_port *port)
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{
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u8 status = mps2_uart_read8(port, UARTn_STATE);
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return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
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}
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static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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}
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static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
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}
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static void mps2_uart_stop_tx(struct uart_port *port)
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{
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u8 control = mps2_uart_read8(port, UARTn_CTRL);
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control &= ~UARTn_CTRL_TX_INT_ENABLE;
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mps2_uart_write8(port, control, UARTn_CTRL);
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}
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static void mps2_uart_tx_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
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if (port->x_char) {
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mps2_uart_write8(port, port->x_char, UARTn_DATA);
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port->x_char = 0;
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port->icount.tx++;
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continue;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port))
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break;
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mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
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xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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mps2_uart_stop_tx(port);
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}
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static void mps2_uart_start_tx(struct uart_port *port)
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{
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u8 control = mps2_uart_read8(port, UARTn_CTRL);
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control |= UARTn_CTRL_TX_INT_ENABLE;
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mps2_uart_write8(port, control, UARTn_CTRL);
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/*
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* We've just unmasked the TX IRQ and now slow-starting via
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* polling; if there is enough data to fill up the internal
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* write buffer in one go, the TX IRQ should assert, at which
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* point we switch to fully interrupt-driven TX.
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*/
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mps2_uart_tx_chars(port);
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}
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static void mps2_uart_stop_rx(struct uart_port *port)
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{
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u8 control = mps2_uart_read8(port, UARTn_CTRL);
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control &= ~UARTn_CTRL_RX_GRP;
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mps2_uart_write8(port, control, UARTn_CTRL);
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}
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static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
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{
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}
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static void mps2_uart_rx_chars(struct uart_port *port)
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{
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struct tty_port *tport = &port->state->port;
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while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
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u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
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port->icount.rx++;
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tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
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}
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tty_flip_buffer_push(tport);
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}
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static irqreturn_t mps2_uart_rxirq(int irq, void *data)
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{
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struct uart_port *port = data;
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u8 irqflag = mps2_uart_read8(port, UARTn_INT);
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if (unlikely(!(irqflag & UARTn_INT_RX)))
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return IRQ_NONE;
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spin_lock(&port->lock);
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mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
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mps2_uart_rx_chars(port);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t mps2_uart_txirq(int irq, void *data)
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{
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struct uart_port *port = data;
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u8 irqflag = mps2_uart_read8(port, UARTn_INT);
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if (unlikely(!(irqflag & UARTn_INT_TX)))
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return IRQ_NONE;
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spin_lock(&port->lock);
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mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
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mps2_uart_tx_chars(port);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
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{
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irqreturn_t handled = IRQ_NONE;
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struct uart_port *port = data;
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u8 irqflag = mps2_uart_read8(port, UARTn_INT);
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spin_lock(&port->lock);
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if (irqflag & UARTn_INT_RX_OVERRUN) {
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struct tty_port *tport = &port->state->port;
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mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
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port->icount.overrun++;
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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tty_flip_buffer_push(tport);
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handled = IRQ_HANDLED;
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}
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/*
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* It's never been seen in practice and it never *should* happen since
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* we check if there is enough room in TX buffer before sending data.
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* So we keep this check in case something suspicious has happened.
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*/
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if (irqflag & UARTn_INT_TX_OVERRUN) {
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mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
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handled = IRQ_HANDLED;
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}
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spin_unlock(&port->lock);
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return handled;
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}
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static int mps2_uart_startup(struct uart_port *port)
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{
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struct mps2_uart_port *mps_port = to_mps2_port(port);
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u8 control = mps2_uart_read8(port, UARTn_CTRL);
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int ret;
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control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
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mps2_uart_write8(port, control, UARTn_CTRL);
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ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0,
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MAKE_NAME(-rx), mps_port);
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if (ret) {
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dev_err(port->dev, "failed to register rxirq (%d)\n", ret);
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return ret;
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}
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ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0,
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MAKE_NAME(-tx), mps_port);
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if (ret) {
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dev_err(port->dev, "failed to register txirq (%d)\n", ret);
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goto err_free_rxirq;
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}
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ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED,
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MAKE_NAME(-overrun), mps_port);
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if (ret) {
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dev_err(port->dev, "failed to register oerrirq (%d)\n", ret);
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goto err_free_txirq;
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}
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control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP;
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mps2_uart_write8(port, control, UARTn_CTRL);
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return 0;
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err_free_txirq:
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free_irq(mps_port->tx_irq, mps_port);
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err_free_rxirq:
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free_irq(mps_port->rx_irq, mps_port);
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return ret;
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}
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static void mps2_uart_shutdown(struct uart_port *port)
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{
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struct mps2_uart_port *mps_port = to_mps2_port(port);
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u8 control = mps2_uart_read8(port, UARTn_CTRL);
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control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP);
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mps2_uart_write8(port, control, UARTn_CTRL);
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free_irq(mps_port->rx_irq, mps_port);
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free_irq(mps_port->tx_irq, mps_port);
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free_irq(port->irq, mps_port);
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}
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static void
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mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned long flags;
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unsigned int baud, bauddiv;
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termios->c_cflag &= ~(CRTSCTS | CMSPAR);
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termios->c_cflag &= ~CSIZE;
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termios->c_cflag |= CS8;
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termios->c_cflag &= ~PARENB;
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termios->c_cflag &= ~CSTOPB;
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baud = uart_get_baud_rate(port, termios, old,
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DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK),
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DIV_ROUND_CLOSEST(port->uartclk, 16));
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bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
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spin_lock_irqsave(&port->lock, flags);
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uart_update_timeout(port, termios->c_cflag, baud);
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mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV);
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spin_unlock_irqrestore(&port->lock, flags);
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if (tty_termios_baud_rate(termios))
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tty_termios_encode_baud_rate(termios, baud, baud);
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}
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static const char *mps2_uart_type(struct uart_port *port)
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{
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return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL;
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}
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static void mps2_uart_release_port(struct uart_port *port)
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{
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}
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static int mps2_uart_request_port(struct uart_port *port)
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{
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return 0;
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}
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static void mps2_uart_config_port(struct uart_port *port, int type)
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{
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if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port))
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port->type = PORT_MPS2UART;
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}
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static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo)
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{
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return -EINVAL;
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}
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static const struct uart_ops mps2_uart_pops = {
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.tx_empty = mps2_uart_tx_empty,
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.set_mctrl = mps2_uart_set_mctrl,
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.get_mctrl = mps2_uart_get_mctrl,
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.stop_tx = mps2_uart_stop_tx,
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.start_tx = mps2_uart_start_tx,
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.stop_rx = mps2_uart_stop_rx,
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.break_ctl = mps2_uart_break_ctl,
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.startup = mps2_uart_startup,
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.shutdown = mps2_uart_shutdown,
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.set_termios = mps2_uart_set_termios,
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.type = mps2_uart_type,
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.release_port = mps2_uart_release_port,
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.request_port = mps2_uart_request_port,
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.config_port = mps2_uart_config_port,
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.verify_port = mps2_uart_verify_port,
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};
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static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS];
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#ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE
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static void mps2_uart_console_putchar(struct uart_port *port, int ch)
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{
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while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)
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cpu_relax();
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mps2_uart_write8(port, ch, UARTn_DATA);
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}
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static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt)
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{
|
||||
struct uart_port *port = &mps2_uart_ports[co->index].port;
|
||||
|
||||
uart_console_write(port, s, cnt, mps2_uart_console_putchar);
|
||||
}
|
||||
|
||||
static int mps2_uart_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct mps2_uart_port *mps_port;
|
||||
int baud = 9600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
if (co->index < 0 || co->index >= MPS2_MAX_PORTS)
|
||||
return -ENODEV;
|
||||
|
||||
mps_port = &mps2_uart_ports[co->index];
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(&mps_port->port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct uart_driver mps2_uart_driver;
|
||||
|
||||
static struct console mps2_uart_console = {
|
||||
.name = SERIAL_NAME,
|
||||
.device = uart_console_device,
|
||||
.write = mps2_uart_console_write,
|
||||
.setup = mps2_uart_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &mps2_uart_driver,
|
||||
};
|
||||
|
||||
#define MPS2_SERIAL_CONSOLE (&mps2_uart_console)
|
||||
|
||||
#else
|
||||
#define MPS2_SERIAL_CONSOLE NULL
|
||||
#endif
|
||||
|
||||
static struct uart_driver mps2_uart_driver = {
|
||||
.driver_name = DRIVER_NAME,
|
||||
.dev_name = SERIAL_NAME,
|
||||
.nr = MPS2_MAX_PORTS,
|
||||
.cons = MPS2_SERIAL_CONSOLE,
|
||||
};
|
||||
|
||||
static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
int id;
|
||||
|
||||
if (!np)
|
||||
return NULL;
|
||||
|
||||
id = of_alias_get_id(np, "serial");
|
||||
if (id < 0)
|
||||
id = 0;
|
||||
|
||||
if (WARN_ON(id >= MPS2_MAX_PORTS))
|
||||
return NULL;
|
||||
|
||||
mps2_uart_ports[id].port.line = id;
|
||||
return &mps2_uart_ports[id];
|
||||
}
|
||||
|
||||
static int mps2_init_port(struct mps2_uart_port *mps_port,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mps_port->port.membase))
|
||||
return PTR_ERR(mps_port->port.membase);
|
||||
|
||||
mps_port->port.mapbase = res->start;
|
||||
mps_port->port.mapsize = resource_size(res);
|
||||
|
||||
mps_port->rx_irq = platform_get_irq(pdev, 0);
|
||||
mps_port->tx_irq = platform_get_irq(pdev, 1);
|
||||
mps_port->port.irq = platform_get_irq(pdev, 2);
|
||||
|
||||
mps_port->port.iotype = UPIO_MEM;
|
||||
mps_port->port.flags = UPF_BOOT_AUTOCONF;
|
||||
mps_port->port.fifosize = 1;
|
||||
mps_port->port.ops = &mps2_uart_pops;
|
||||
mps_port->port.dev = &pdev->dev;
|
||||
|
||||
mps_port->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(mps_port->clk))
|
||||
return PTR_ERR(mps_port->clk);
|
||||
|
||||
ret = clk_prepare_enable(mps_port->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mps_port->port.uartclk = clk_get_rate(mps_port->clk);
|
||||
|
||||
clk_disable_unprepare(mps_port->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mps2_serial_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mps2_uart_port *mps_port;
|
||||
int ret;
|
||||
|
||||
mps_port = mps2_of_get_port(pdev);
|
||||
if (!mps_port)
|
||||
return -ENODEV;
|
||||
|
||||
ret = mps2_init_port(mps_port, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, mps_port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mps2_serial_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mps2_uart_port *mps_port = platform_get_drvdata(pdev);
|
||||
|
||||
uart_remove_one_port(&mps2_uart_driver, &mps_port->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id mps2_match[] = {
|
||||
{ .compatible = "arm,mps2-uart", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mps2_match);
|
||||
#endif
|
||||
|
||||
static struct platform_driver mps2_serial_driver = {
|
||||
.probe = mps2_serial_probe,
|
||||
.remove = mps2_serial_remove,
|
||||
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = of_match_ptr(mps2_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mps2_uart_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&mps2_uart_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&mps2_serial_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&mps2_uart_driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
module_init(mps2_uart_init);
|
||||
|
||||
static void __exit mps2_uart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mps2_serial_driver);
|
||||
uart_unregister_driver(&mps2_uart_driver);
|
||||
}
|
||||
module_exit(mps2_uart_exit);
|
||||
|
||||
MODULE_AUTHOR("Vladimir Murzin <vladimir.murzin@arm.com>");
|
||||
MODULE_DESCRIPTION("MPS2 UART driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
|
|
@ -264,4 +264,7 @@
|
|||
/* MVEBU UART */
|
||||
#define PORT_MVEBU 114
|
||||
|
||||
/* MPS2 UART */
|
||||
#define PORT_MPS2UART 115
|
||||
|
||||
#endif /* _UAPILINUX_SERIAL_CORE_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue