drm/amdgpu: Hardcode virtual DCE vblank / scanout position return values
For virtual display feature, by hardcoding 0 for the vblank counter and -EINVAL for the scanout position return value, we signal to the core DRM code that there are no hardware counters we can use for these. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -55,10 +55,7 @@ static void dce_virtual_vblank_wait(struct amdgpu_device *adev, int crtc)
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static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
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static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
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{
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{
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if (crtc >= adev->mode_info.num_crtc)
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return 0;
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return 0;
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else
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return adev->ddev->vblank[crtc].count;
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}
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}
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static void dce_virtual_page_flip(struct amdgpu_device *adev,
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static void dce_virtual_page_flip(struct amdgpu_device *adev,
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@ -70,13 +67,10 @@ static void dce_virtual_page_flip(struct amdgpu_device *adev,
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static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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u32 *vbl, u32 *position)
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u32 *vbl, u32 *position)
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{
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{
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if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
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return -EINVAL;
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*vbl = 0;
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*vbl = 0;
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*position = 0;
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*position = 0;
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return 0;
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return -EINVAL;
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}
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}
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static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
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static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
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@ -407,6 +401,8 @@ static int dce_virtual_sw_init(void *handle)
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if (r)
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if (r)
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return r;
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return r;
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adev->ddev->max_vblank_count = 0;
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adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
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adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
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adev->ddev->mode_config.max_width = 16384;
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adev->ddev->mode_config.max_width = 16384;
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@ -655,7 +651,6 @@ static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vbla
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struct amdgpu_mode_info *mode_info = container_of(vblank_timer, struct amdgpu_mode_info ,vblank_timer);
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struct amdgpu_mode_info *mode_info = container_of(vblank_timer, struct amdgpu_mode_info ,vblank_timer);
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struct amdgpu_device *adev = container_of(mode_info, struct amdgpu_device ,mode_info);
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struct amdgpu_device *adev = container_of(mode_info, struct amdgpu_device ,mode_info);
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unsigned crtc = 0;
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unsigned crtc = 0;
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adev->ddev->vblank[0].count++;
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drm_handle_vblank(adev->ddev, crtc);
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drm_handle_vblank(adev->ddev, crtc);
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dce_virtual_pageflip_irq(adev, NULL, NULL);
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dce_virtual_pageflip_irq(adev, NULL, NULL);
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hrtimer_start(vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL);
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hrtimer_start(vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL);
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@ -682,8 +677,6 @@ static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad
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hrtimer_cancel(&adev->mode_info.vblank_timer);
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hrtimer_cancel(&adev->mode_info.vblank_timer);
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}
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}
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if (!state || (state && !adev->mode_info.vsync_timer_enabled))
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adev->ddev->vblank[0].count = 0;
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adev->mode_info.vsync_timer_enabled = state;
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adev->mode_info.vsync_timer_enabled = state;
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DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
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DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
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}
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}
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@ -720,7 +713,6 @@ static int dce_virtual_crtc_irq(struct amdgpu_device *adev,
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unsigned crtc = 0;
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unsigned crtc = 0;
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unsigned irq_type = AMDGPU_CRTC_IRQ_VBLANK1;
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unsigned irq_type = AMDGPU_CRTC_IRQ_VBLANK1;
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adev->ddev->vblank[crtc].count++;
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dce_virtual_crtc_vblank_int_ack(adev, crtc);
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dce_virtual_crtc_vblank_int_ack(adev, crtc);
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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if (amdgpu_irq_enabled(adev, source, irq_type)) {
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