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RISC-V: Parse cpu topology during boot. 

Currently, there are no topology defined for RISC-V.
Parse the cpu-map node from device tree and setup the
cpu topology.

CPU topology after applying the patch.
$cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-3
$cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list
0-3
$cat /sys/devices/system/cpu/cpu3/topology/physical_package_id
0
$cat /sys/devices/system/cpu/cpu3/topology/core_id
3

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Atish Patra 2019-06-27 12:53:00 -07:00 committed by Paul Walmsley
parent ca74b316df
commit 03f11f03db
2 changed files with 4 additions and 0 deletions
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1
arch/riscv/Kconfig
View File

@ -48,6 +48,7 @@ config RISCV
select PCI_MSI if PCI select PCI_MSI if PCI
select RISCV_TIMER select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_ARCH_TOPOLOGY if SMP
select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_MMIOWB select ARCH_HAS_MMIOWB
select HAVE_EBPF_JIT if 64BIT select HAVE_EBPF_JIT if 64BIT

3
arch/riscv/kernel/smpboot.c
View File

@ -8,6 +8,7 @@
* Copyright (C) 2017 SiFive * Copyright (C) 2017 SiFive
*/ */
#include <linux/arch_topology.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
@ -35,6 +36,7 @@ static DECLARE_COMPLETION(cpu_running);
void __init smp_prepare_boot_cpu(void) void __init smp_prepare_boot_cpu(void)
{ {
init_cpu_topology();
} }
void __init smp_prepare_cpus(unsigned int max_cpus) void __init smp_prepare_cpus(unsigned int max_cpus)
@ -138,6 +140,7 @@ asmlinkage void __init smp_callin(void)
trap_init(); trap_init();
notify_cpu_starting(smp_processor_id()); notify_cpu_starting(smp_processor_id());
update_siblings_masks(smp_processor_id());
set_cpu_online(smp_processor_id(), 1); set_cpu_online(smp_processor_id(), 1);
/* /*
* Remote TLB flushes are ignored while the CPU is offline, so emit * Remote TLB flushes are ignored while the CPU is offline, so emit