From bf513bf04660321eb6181082def79ee1fd93b48f Mon Sep 17 00:00:00 2001
From: Walter Lozano <walter@vanguardiasur.com.ar>
Date: Tue, 21 Apr 2015 00:35:53 -0500
Subject: [PATCH 1/9] ARM: socfpga: dts: Add adxl34x
This patch adds the DTS bindings for the adxl34x digital
accelerometer.
Signed-off-by: Walter Lozano <walter@vanguardiasur.com.ar>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index 16ea6f5f2ab8..71468a7eb28f 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -68,3 +68,19 @@
&usb1 {
status = "okay";
};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c1{
+ status = "okay";
+
+ accel1: accel1@53{
+ compatible = "adxl34x";
+ reg = <0x53>;
+
+ interrupt-parent = < &portc >;
+ interrupts = <3 2>;
+ };
+};
From 08d6638f1a3cf5f6add4ecfd58d28c53b206dbcb Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Mon, 9 Mar 2015 22:41:17 -0500
Subject: [PATCH 2/9] ARM: socfpga: dts: add cpu1-start-addr for Arria 10
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8a05c47fd57f..69d616a05b14 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -284,6 +284,7 @@
sysmgr: sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
+ cpu1-start-addr = <0xffd06230>;
};
/* Local timer */
From 1dfb7d2fd6a8f9c69f0b434473637d88917c9ec7 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Mon, 9 Mar 2015 23:05:21 -0500
Subject: [PATCH 3/9] ARM: socfpga: dts: disable the sdmmc, and uart nodes in
the base arria10
Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart
nodes should be enabled in the appropriate board file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 69d616a05b14..d8436095b1dd 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -268,6 +268,7 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
+ status = "disabled";
};
ocram: sram@ffe00000 {
@@ -324,6 +325,7 @@
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ status = "disabled";
};
uart1: serial1@ffc02100 {
@@ -332,6 +334,7 @@
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ status = "disabled";
};
usbphy0: usbphy@0 {
From 74568da48f69c21c8628090eaedb990369813a0b Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Thu, 2 Apr 2015 13:26:35 -0500
Subject: [PATCH 4/9] ARM: socfpga: dts: enable UART1 for the debug uart
Arria10 devkit is using UART1 for the debug uart port. Remove
unused aliases.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add removal of unused aliases
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ------------
arch/arm/boot/dts/socfpga_arria10_socdk.dts | 8 ++++----
2 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d8436095b1dd..6c3ad9220845 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -21,18 +21,6 @@
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
index 3015ce8d3057..811a61cd9dc7 100755
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -40,9 +40,9 @@
};
};
};
-
- serial0@ffc02000 {
- status = "okay";
- };
};
};
+
+&uart1 {
+ status = "okay";
+};
From 88c8e4c2648c9daa18430a47e746a669254f00e5 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Mon, 9 Mar 2015 22:57:04 -0500
Subject: [PATCH 5/9] ARM: socfpga: dts: rename socdk board file to socdk_sdmmc
Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc
as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus
we will need to have 2 separate board files, one for SDMMC and one for
QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi
so that we use common peripherals for each flavor of the devkits.
Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/Makefile | 2 +-
...0_socdk.dts => socfpga_arria10_socdk.dtsi} | 4 +--
.../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 26 +++++++++++++++++++
3 files changed, 28 insertions(+), 4 deletions(-)
rename arch/arm/boot/dts/{socfpga_arria10_socdk.dts => socfpga_arria10_socdk.dtsi} (94%)
mode change 100755 => 100644
create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 86217db2937a..2ce74f10860a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -496,7 +496,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
- socfpga_arria10_socdk.dtb \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
old mode 100755
new mode 100644
similarity index 94%
rename from arch/arm/boot/dts/socfpga_arria10_socdk.dts
rename to arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 811a61cd9dc7..347ca4ef58f8
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,8 +14,6 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-
-/dts-v1/;
#include "socfpga_arria10.dtsi"
/ {
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
new file mode 100644
index 000000000000..dbbb751ac1ba
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&mmc {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+};
From 5459f9abe24c810e09d012519788747e97b3cdd7 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Fri, 10 Apr 2015 15:40:42 -0500
Subject: [PATCH 6/9] ARM: socfpga: dts: Add a clock node for sdmmc CIU
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock
which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk
passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided
node and makes the sdmmc_clk it's parent.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: renamed ciu_clk to sdmmc_clk_divided
---
arch/arm/boot/dts/socfpga.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index d9176e606173..be4beda11d3d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -451,6 +451,14 @@
clk-phase = <0 135>;
};
+ sdmmc_clk_divided: sdmmc_clk_divided {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&sdmmc_clk>;
+ clk-gate = <0xa0 8>;
+ fixed-divider = <4>;
+ };
+
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
@@ -635,7 +643,7 @@
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
};
From be9863cac24b53e826ded959ae4747a6f388885f Mon Sep 17 00:00:00 2001
From: Vince Bridgers <vbridger@opensource.altera.com>
Date: Tue, 21 Apr 2015 14:15:40 -0500
Subject: [PATCH 7/9] ARM: socfpga: dts: Add multicast bins and unicast filter
entries
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 6c3ad9220845..38c643d620c4 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -116,6 +116,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
status = "disabled";
};
@@ -126,6 +128,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
status = "disabled";
};
@@ -136,6 +140,8 @@
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
status = "disabled";
};
From c01e8cdb7bf52681530d1a6ac3474c070468983b Mon Sep 17 00:00:00 2001
From: Vince Bridgers <vbridger@opensource.altera.com>
Date: Tue, 21 Apr 2015 14:19:24 -0500
Subject: [PATCH 8/9] ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth
properties
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga
stmmac. These devicetree properties will be used to configure certain
features of the stmmac on the socfpga.
Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 4 ++++
arch/arm/boot/dts/socfpga_arria10.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index be4beda11d3d..2e9ed36df12e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -496,6 +496,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -512,6 +514,8 @@
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 38c643d620c4..ab0af2afdcf7 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -130,6 +130,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <16384>;
status = "disabled";
};
@@ -142,6 +144,8 @@
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <16384>;
status = "disabled";
};
From da29d824a6709116dd4dc50b82400547447a4f53 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Thu, 2 Apr 2015 11:43:20 -0500
Subject: [PATCH 9/9] ARM: socfpga: dts: add clocks to the Arria10 platform
Add all the clock nodes for the Arria10 platform. At the same time, update
the peripherals with their respective clocks property.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: Add the l4_sys_free_clk node
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 309 ++++++++++++++++++++++++-
1 file changed, 305 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index ab0af2afdcf7..abf97630c592 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -86,6 +86,21 @@
#address-cells = <1>;
#size-cells = <0>;
+ cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb_intosc_ls_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s_free_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -95,16 +110,286 @@
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc1>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>;
+ reg = <0x40>;
+
+ main_mpu_base_clk: main_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x140 0 11>;
+ };
+
+ main_noc_base_clk: main_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x144 0 11>;
+ };
+
+ main_emaca_clk: main_emaca_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x68>;
+ };
+
+ main_emacb_clk: main_emacb_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x6C>;
+ };
+
+ main_emac_ptp_clk: main_emac_ptp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x70>;
+ };
+
+ main_gpio_db_clk: main_gpio_db_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x74>;
+ };
+
+ main_sdmmc_clk: main_sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk"
+;
+ clocks = <&main_pll>;
+ reg = <0x78>;
+ };
+
+ main_s2f_usr0_clk: main_s2f_usr0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x7C>;
+ };
+
+ main_s2f_usr1_clk: main_s2f_usr1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x80>;
+ };
+
+ main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x84>;
+ };
+
+ main_periph_ref_clk: main_periph_ref_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x9C>;
+ };
};
periph_pll: periph_pll {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc1>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>, <&main_periph_ref_clk>;
+ reg = <0xC0>;
+
+ peri_mpu_base_clk: peri_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x140 16 11>;
+ };
+
+ peri_noc_base_clk: peri_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x144 16 11>;
+ };
+
+ peri_emaca_clk: peri_emaca_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xE8>;
+ };
+
+ peri_emacb_clk: peri_emacb_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xEC>;
+ };
+
+ peri_emac_ptp_clk: peri_emac_ptp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF0>;
+ };
+
+ peri_gpio_db_clk: peri_gpio_db_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF4>;
+ };
+
+ peri_sdmmc_clk: peri_sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF8>;
+ };
+
+ peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xFC>;
+ };
+
+ peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x100>;
+ };
+
+ peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x104>;
+ };
+ };
+
+ mpu_free_clk: mpu_free_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x60>;
+ };
+
+ noc_free_clk: noc_free_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x64>;
+ };
+
+ s2f_user1_free_clk: s2f_user1_free_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x104>;
+ };
+
+ sdmmc_free_clk: sdmmc_free_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ fixed-divider = <4>;
+ reg = <0xF8>;
+ };
+
+ l4_sys_free_clk: l4_sys_free_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&noc_free_clk>;
+ fixed-divider = <4>;
+ };
+
+ l4_main_clk: l4_main_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 0 2>;
+ clk-gate = <0x48 1>;
+ };
+
+ l4_mp_clk: l4_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 8 2>;
+ clk-gate = <0x48 2>;
+ };
+
+ l4_sp_clk: l4_sp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 16 2>;
+ clk-gate = <0x48 3>;
+ };
+
+ mpu_periph_clk: mpu_periph_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&mpu_free_clk>;
+ fixed-divider = <4>;
+ clk-gate = <0x48 0>;
+ };
+
+ sdmmc_clk: sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&sdmmc_free_clk>;
+ clk-gate = <0xC8 5>;
+ };
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 11>;
+ };
+
+ nand_clk: nand_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 10>;
+ };
+
+ spi_m_clk: spi_m_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 9>;
+ };
+
+ usb_clk: usb_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 8>;
+ };
+
+ s2f_usr1_clk: s2f_usr1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&peri_s2f_usr1_clk>;
+ clk-gate = <0xC8 6>;
};
};
};
@@ -266,6 +551,8 @@
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
+ clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
+ clock-names = "biu", "ciu";
status = "disabled";
};
@@ -291,30 +578,39 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
interrupts = <1 13 0xf04>;
+ clocks = <&mpu_periph_clk>;
};
timer0: timer0@ffc02700 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02700 0x100>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
};
timer1: timer1@ffc02800 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02800 0x100>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd00000 0x100>;
+ clocks = <&l4_sys_free_clk>;
+ clock-names = "timer";
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>;
+ clocks = <&l4_sys_free_clk>;
+ clock-names = "timer";
};
uart0: serial0@ffc02000 {
@@ -332,6 +628,7 @@
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
status = "disabled";
};
@@ -345,6 +642,8 @@
compatible = "snps,dwc2";
reg = <0xffb00000 0xffff>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_clk>;
+ clock-names = "otg";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -363,6 +662,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
@@ -370,6 +670,7 @@
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
};