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drm/nouveau/fb: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 151abd44c2
commit 03c8952fb3
47 changed files with 654 additions and 818 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvif/device.h
View File

@ -51,7 +51,7 @@ u64 nvif_device_time(struct nvif_device *);
nv_device(_device->object.priv); \
})
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvkm_fb(nvxx_device(a))
#define nvxx_fb(a) nvxx_device(a)->fb
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
#define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))

72
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
View File

@ -46,59 +46,47 @@ struct nvkm_fb_tile {
};
struct nvkm_fb {
const struct nvkm_fb_func *func;
struct nvkm_subdev subdev;
bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
struct nvkm_ram *ram;
struct {
struct nvkm_fb_tile region[16];
int regions;
void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
} tile;
};
static inline struct nvkm_fb *
nvkm_fb(void *obj)
{
/* fbram uses this before device subdev pointer is valid */
if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
nv_subidx(obj) == NVDEV_SUBDEV_FB)
return obj;
bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
void nvkm_fb_tile_init(struct nvkm_fb *, int region, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nvkm_fb_tile_fini(struct nvkm_fb *, int region, struct nvkm_fb_tile *);
void nvkm_fb_tile_prog(struct nvkm_fb *, int region, struct nvkm_fb_tile *);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB);
}
extern struct nvkm_oclass *nv04_fb_oclass;
extern struct nvkm_oclass *nv10_fb_oclass;
extern struct nvkm_oclass *nv1a_fb_oclass;
extern struct nvkm_oclass *nv20_fb_oclass;
extern struct nvkm_oclass *nv25_fb_oclass;
extern struct nvkm_oclass *nv30_fb_oclass;
extern struct nvkm_oclass *nv35_fb_oclass;
extern struct nvkm_oclass *nv36_fb_oclass;
extern struct nvkm_oclass *nv40_fb_oclass;
extern struct nvkm_oclass *nv41_fb_oclass;
extern struct nvkm_oclass *nv44_fb_oclass;
extern struct nvkm_oclass *nv46_fb_oclass;
extern struct nvkm_oclass *nv47_fb_oclass;
extern struct nvkm_oclass *nv49_fb_oclass;
extern struct nvkm_oclass *nv4e_fb_oclass;
extern struct nvkm_oclass *nv50_fb_oclass;
extern struct nvkm_oclass *g84_fb_oclass;
extern struct nvkm_oclass *gt215_fb_oclass;
extern struct nvkm_oclass *mcp77_fb_oclass;
extern struct nvkm_oclass *mcp89_fb_oclass;
extern struct nvkm_oclass *gf100_fb_oclass;
extern struct nvkm_oclass *gk104_fb_oclass;
extern struct nvkm_oclass *gk20a_fb_oclass;
extern struct nvkm_oclass *gm107_fb_oclass;
int nv04_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv10_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv1a_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv20_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv25_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv30_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv35_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv36_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv40_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv41_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv44_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv46_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv47_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv49_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv4e_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int nv50_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int g84_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gt215_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int mcp77_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int mcp89_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gf100_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gk104_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gk20a_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
int gm107_fb_new(struct nvkm_device *, int, struct nvkm_fb **);
#include <subdev/bios.h>
#include <subdev/bios/ramcfg.h>

12
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -50,22 +50,16 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
int i = reg - drm->tile.reg;
struct nvkm_fb *fb = nvxx_fb(&drm->device);
struct nvkm_fb_tile *tile = &fb->tile.region[i];
struct nvkm_engine *engine;
nouveau_fence_unref(&reg->fence);
if (tile->pitch)
fb->tile.fini(fb, i, tile);
nvkm_fb_tile_fini(fb, i, tile);
if (pitch)
fb->tile.init(fb, i, addr, size, pitch, flags, tile);
nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
fb->tile.prog(fb, i, tile);
if ((engine = nvkm_engine(fb, NVDEV_ENGINE_GR)))
engine->tile_prog(engine, i);
if ((engine = nvkm_engine(fb, NVDEV_ENGINE_MPEG)))
engine->tile_prog(engine, i);
nvkm_fb_tile_prog(fb, i, tile);
}
static struct nouveau_drm_tile *

2
drivers/gpu/drm/nouveau/nouveau_gem.c
View File

@ -259,7 +259,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
struct nouveau_bo *nvbo = NULL;
int ret = 0;
if (!fb->memtype_valid(fb, req->info.tile_flags)) {
if (!nvkm_fb_memtype_valid(fb, req->info.tile_flags)) {
NV_PRINTK(err, cli, "bad page flags: 0x%08x\n", req->info.tile_flags);
return -EINVAL;
}

138
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -80,7 +80,7 @@ nv4_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
.fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
@ -100,7 +100,7 @@ nv5_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
.fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
@ -120,7 +120,7 @@ nv10_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -139,7 +139,7 @@ nv11_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -160,7 +160,7 @@ nv15_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -181,7 +181,7 @@ nv17_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -202,7 +202,7 @@ nv18_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -223,7 +223,7 @@ nv1a_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
.fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -244,7 +244,7 @@ nv1f_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
.fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -265,7 +265,7 @@ nv20_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
.fb = nv20_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -286,7 +286,7 @@ nv25_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
.fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -307,7 +307,7 @@ nv28_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
.fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -328,7 +328,7 @@ nv2a_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
.fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -349,7 +349,7 @@ nv30_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
.fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -370,7 +370,7 @@ nv31_chipset = {
.bus = nv31_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
.fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -392,7 +392,7 @@ nv34_chipset = {
.bus = nv31_bus_new,
.clk = nv04_clk_new,
.devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
.fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -414,7 +414,7 @@ nv35_chipset = {
.bus = nv04_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
.fb = nv35_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -435,7 +435,7 @@ nv36_chipset = {
.bus = nv31_bus_new,
.clk = nv04_clk_new,
.devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
.fb = nv36_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
@ -457,7 +457,7 @@ nv40_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
.fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -482,7 +482,7 @@ nv41_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
.fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -507,7 +507,7 @@ nv42_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
.fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -532,7 +532,7 @@ nv43_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
.fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -557,7 +557,7 @@ nv44_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
.fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -582,7 +582,7 @@ nv45_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
.fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -607,7 +607,7 @@ nv46_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -632,7 +632,7 @@ nv47_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
.fb = nv47_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -657,7 +657,7 @@ nv49_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
.fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -682,7 +682,7 @@ nv4a_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
.fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -707,7 +707,7 @@ nv4b_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
.fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -732,7 +732,7 @@ nv4c_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -757,7 +757,7 @@ nv4e_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
.fb = nv4e_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv4e_i2c_new,
// .imem = nv40_instmem_new,
@ -783,7 +783,7 @@ nv50_chipset = {
.bus = nv50_bus_new,
.clk = nv50_clk_new,
.devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
.fb = nv50_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
@ -810,7 +810,7 @@ nv63_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -835,7 +835,7 @@ nv67_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -860,7 +860,7 @@ nv68_chipset = {
.bus = nv31_bus_new,
.clk = nv40_clk_new,
.devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
.fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
@ -886,7 +886,7 @@ nv84_chipset = {
.bus = nv50_bus_new,
.clk = g84_clk_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
@ -917,7 +917,7 @@ nv86_chipset = {
.bus = nv50_bus_new,
.clk = g84_clk_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
@ -948,7 +948,7 @@ nv92_chipset = {
.bus = nv50_bus_new,
.clk = g84_clk_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
@ -979,7 +979,7 @@ nv94_chipset = {
.bus = g94_bus_new,
.clk = g84_clk_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1016,7 +1016,7 @@ nv96_chipset = {
// .mc = g94_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.bar = g84_bar_new,
@ -1047,7 +1047,7 @@ nv98_chipset = {
// .mc = g98_mc_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.bar = g84_bar_new,
@ -1072,7 +1072,7 @@ nva0_chipset = {
.bus = g94_bus_new,
.clk = g84_clk_new,
.devinit = g84_devinit_new,
// .fb = g84_fb_new,
.fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = nv50_i2c_new,
@ -1103,7 +1103,7 @@ nva3_chipset = {
.bus = g94_bus_new,
.clk = gt215_clk_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1136,7 +1136,7 @@ nva5_chipset = {
.bus = g94_bus_new,
.clk = gt215_clk_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1168,7 +1168,7 @@ nva8_chipset = {
.bus = g94_bus_new,
.clk = gt215_clk_new,
.devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
.fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1200,7 +1200,7 @@ nvaa_chipset = {
.bus = g94_bus_new,
.clk = mcp77_clk_new,
.devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
.fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1231,7 +1231,7 @@ nvac_chipset = {
.bus = g94_bus_new,
.clk = mcp77_clk_new,
.devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
.fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1262,7 +1262,7 @@ nvaf_chipset = {
.bus = g94_bus_new,
.clk = gt215_clk_new,
.devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
.fb = mcp89_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1294,7 +1294,7 @@ nvc0_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1329,7 +1329,7 @@ nvc1_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1363,7 +1363,7 @@ nvc3_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1397,7 +1397,7 @@ nvc4_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1432,7 +1432,7 @@ nvc8_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1467,7 +1467,7 @@ nvce_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1502,7 +1502,7 @@ nvcf_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
@ -1536,7 +1536,7 @@ nvd7_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
// .i2c = gf117_i2c_new,
@ -1568,7 +1568,7 @@ nvd9_chipset = {
.bus = gf100_bus_new,
.clk = gf100_clk_new,
.devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
.fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
// .i2c = gf110_i2c_new,
@ -1602,7 +1602,7 @@ nve4_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1638,7 +1638,7 @@ nve6_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1674,7 +1674,7 @@ nve7_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1708,7 +1708,7 @@ nvea_chipset = {
.bar = gk20a_bar_new,
.bus = gf100_bus_new,
.clk = gk20a_clk_new,
// .fb = gk20a_fb_new,
.fb = gk20a_fb_new,
// .fuse = gf100_fuse_new,
// .ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,
@ -1734,7 +1734,7 @@ nvf0_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1770,7 +1770,7 @@ nvf1_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
@ -1806,7 +1806,7 @@ nv106_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1841,7 +1841,7 @@ nv108_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
.fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
@ -1876,7 +1876,7 @@ nv117_chipset = {
.bus = gf100_bus_new,
.clk = gk104_clk_new,
.devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
.fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
@ -1905,7 +1905,7 @@ nv124_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
.fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
@ -1934,7 +1934,7 @@ nv126_chipset = {
.bios = nvkm_bios_new,
.bus = gf100_bus_new,
.devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
.fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
@ -1961,7 +1961,7 @@ nv12b_chipset = {
.name = "GM20B",
.bar = gk20a_bar_new,
.bus = gf100_bus_new,
// .fb = gk20a_fb_new,
.fb = gk20a_fb_new,
// .fuse = gm107_fuse_new,
// .ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -35,7 +35,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -62,7 +61,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -89,7 +87,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -115,7 +112,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -142,7 +138,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -168,7 +163,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -194,7 +188,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -221,7 +214,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -247,7 +239,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -35,7 +35,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -63,7 +62,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -91,7 +89,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -115,7 +112,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
@ -137,7 +133,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -165,7 +160,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -193,7 +187,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -220,7 +213,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -35,7 +35,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -73,7 +72,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -108,7 +106,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -137,7 +134,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -31,7 +31,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -44,7 +43,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -32,7 +32,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -44,7 +43,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -58,7 +56,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -72,7 +69,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -86,7 +82,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -100,7 +95,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -114,7 +108,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -128,7 +121,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -32,7 +32,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -46,7 +45,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -60,7 +58,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -74,7 +71,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -32,7 +32,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -46,7 +45,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -60,7 +58,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -75,7 +72,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -90,7 +86,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -33,7 +33,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -51,7 +50,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -69,7 +67,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -87,7 +84,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -105,7 +101,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -123,7 +118,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -141,7 +135,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -159,7 +152,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -177,7 +169,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -195,7 +186,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -213,7 +203,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -231,7 +220,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -249,7 +237,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -267,7 +254,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -285,7 +271,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -303,7 +288,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -35,7 +35,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -55,7 +54,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -78,7 +76,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -101,7 +98,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -124,7 +120,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -147,7 +142,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -170,7 +164,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -193,7 +186,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -216,7 +208,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -239,7 +230,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -262,7 +252,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -287,7 +276,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -311,7 +299,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
@ -335,7 +322,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
View File

@ -569,7 +569,7 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx)
else if (device->chipset < 0xa0)
gr_def(ctx, 0x407d08, 0x00390040);
else {
if (nvkm_fb(device)->ram->type != NVKM_RAM_TYPE_GDDR5)
if (device->fb->ram->type != NVKM_RAM_TYPE_GDDR5)
gr_def(ctx, 0x407d08, 0x003d0040);
else
gr_def(ctx, 0x407d08, 0x003c0040);

144
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
View File

@ -26,6 +26,38 @@
#include <subdev/bios.h>
#include <subdev/bios/M0203.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
bool
nvkm_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype)
{
return fb->func->memtype_valid(fb, memtype);
}
void
nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
{
fb->func->tile.fini(fb, region, tile);
}
void
nvkm_fb_tile_init(struct nvkm_fb *fb, int region, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *tile)
{
fb->func->tile.init(fb, region, addr, size, pitch, flags, tile);
}
void
nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
{
struct nvkm_device *device = fb->subdev.device;
fb->func->tile.prog(fb, region, tile);
if (likely(device->gr))
device->gr->engine.tile_prog(&device->gr->engine, region);
if (likely(device->mpeg))
device->mpeg->tile_prog(device->mpeg, region);
}
int
nvkm_fb_bios_memtype(struct nvkm_bios *bios)
@ -52,69 +84,87 @@ nvkm_fb_bios_memtype(struct nvkm_bios *bios)
return NVKM_RAM_TYPE_UNKNOWN;
}
int
_nvkm_fb_fini(struct nvkm_object *object, bool suspend)
static void
nvkm_fb_intr(struct nvkm_subdev *subdev)
{
struct nvkm_fb *fb = (void *)object;
return nvkm_subdev_fini_old(&fb->subdev, suspend);
struct nvkm_fb *fb = nvkm_fb(subdev);
if (fb->func->intr)
fb->func->intr(fb);
}
int
_nvkm_fb_init(struct nvkm_object *object)
static int
nvkm_fb_oneinit(struct nvkm_subdev *subdev)
{
struct nvkm_fb *fb = (void *)object;
int ret, i;
ret = nvkm_subdev_init_old(&fb->subdev);
if (ret)
return ret;
if (fb->ram)
nvkm_ram_init(fb->ram);
for (i = 0; i < fb->tile.regions; i++)
fb->tile.prog(fb, i, &fb->tile.region[i]);
struct nvkm_fb *fb = nvkm_fb(subdev);
if (fb->func->ram_new) {
int ret = fb->func->ram_new(fb, &fb->ram);
if (ret) {
nvkm_error(subdev, "vram setup failed, %d\n", ret);
return ret;
}
}
return 0;
}
void
_nvkm_fb_dtor(struct nvkm_object *object)
static int
nvkm_fb_init(struct nvkm_subdev *subdev)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_fb *fb = nvkm_fb(subdev);
int ret, i;
if (fb->ram) {
ret = nvkm_ram_init(fb->ram);
if (ret)
return ret;
}
for (i = 0; i < fb->tile.regions; i++)
fb->func->tile.prog(fb, i, &fb->tile.region[i]);
if (fb->func->init)
fb->func->init(fb);
return 0;
}
static void *
nvkm_fb_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_fb *fb = nvkm_fb(subdev);
int i;
for (i = 0; i < fb->tile.regions; i++)
fb->tile.fini(fb, i, &fb->tile.region[i]);
fb->func->tile.fini(fb, i, &fb->tile.region[i]);
nvkm_ram_del(&fb->ram);
nvkm_subdev_destroy(&fb->subdev);
if (fb->func->dtor)
return fb->func->dtor(fb);
return fb;
}
static const struct nvkm_subdev_func
nvkm_fb = {
.dtor = nvkm_fb_dtor,
.oneinit = nvkm_fb_oneinit,
.init = nvkm_fb_init,
.intr = nvkm_fb_intr,
};
void
nvkm_fb_ctor(const struct nvkm_fb_func *func, struct nvkm_device *device,
int index, struct nvkm_fb *fb)
{
nvkm_subdev_ctor(&nvkm_fb, device, index, 0, &fb->subdev);
fb->func = func;
fb->tile.regions = fb->func->tile.regions;
}
int
nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject)
nvkm_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
int index, struct nvkm_fb **pfb)
{
struct nvkm_fb_impl *impl = (void *)oclass;
struct nvkm_fb *fb;
int ret;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
length, pobject);
fb = *pobject;
if (ret)
return ret;
fb->memtype_valid = impl->memtype;
if (!impl->ram_new)
return 0;
ret = impl->ram_new(fb, &fb->ram);
if (ret) {
nvkm_error(&fb->subdev, "vram init failed, %d\n", ret);
return ret;
}
if (!(*pfb = kzalloc(sizeof(**pfb), GFP_KERNEL)))
return -ENOMEM;
nvkm_fb_ctor(func, device, index, *pfb);
return 0;
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c
View File

@ -24,16 +24,14 @@
#include "nv50.h"
#include "ram.h"
struct nvkm_oclass *
g84_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x84),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram_new = nv50_ram_new,
static const struct nv50_fb_func
g84_fb = {
.ram_new = nv50_ram_new,
.trap = 0x001d07ff,
}.base.base;
};
int
g84_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nv50_fb_new_(&g84_fb, device, index, pfb);
}

68
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
View File

@ -33,9 +33,11 @@ gf100_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags)
return likely((gf100_pte_storage_type_map[memtype] != 0xff));
}
static void
gf100_fb_intr(struct nvkm_subdev *subdev)
void
gf100_fb_intr(struct nvkm_fb *base)
{
struct gf100_fb *fb = gf100_fb(base);
struct nvkm_subdev *subdev = &fb->base.subdev;
struct nvkm_device *device = subdev->device;
u32 intr = nvkm_rd32(device, 0x000100);
if (intr & 0x08000000)
@ -44,29 +46,23 @@ gf100_fb_intr(struct nvkm_subdev *subdev)
nvkm_debug(subdev, "PBFB intr\n");
}
int
gf100_fb_init(struct nvkm_object *object)
void
gf100_fb_init(struct nvkm_fb *base)
{
struct gf100_fb *fb = (void *)object;
struct gf100_fb *fb = gf100_fb(base);
struct nvkm_device *device = fb->base.subdev.device;
int ret;
ret = nvkm_fb_init(&fb->base);
if (ret)
return ret;
if (fb->r100c10_page)
nvkm_wr32(device, 0x100c10, fb->r100c10 >> 8);
nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
return 0;
}
void
gf100_fb_dtor(struct nvkm_object *object)
void *
gf100_fb_dtor(struct nvkm_fb *base)
{
struct nvkm_device *device = nv_device(object);
struct gf100_fb *fb = (void *)object;
struct gf100_fb *fb = gf100_fb(base);
struct nvkm_device *device = fb->base.subdev.device;
if (fb->r100c10_page) {
dma_unmap_page(nv_device_base(device), fb->r100c10, PAGE_SIZE,
@ -74,22 +70,19 @@ gf100_fb_dtor(struct nvkm_object *object)
__free_page(fb->r100c10_page);
}
nvkm_fb_destroy(&fb->base);
return fb;
}
int
gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device,
int index, struct nvkm_fb **pfb)
{
struct nvkm_device *device = nv_device(parent);
struct gf100_fb *fb;
int ret;
ret = nvkm_fb_create(parent, engine, oclass, &fb);
*pobject = nv_object(fb);
if (ret)
return ret;
if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
return -ENOMEM;
nvkm_fb_ctor(func, device, index, &fb->base);
*pfb = &fb->base;
fb->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
if (fb->r100c10_page) {
@ -100,19 +93,20 @@ gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return -EFAULT;
}
nv_subdev(fb)->intr = gf100_fb_intr;
return 0;
}
struct nvkm_oclass *
gf100_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_fb_ctor,
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.fini = _nvkm_fb_fini,
},
.memtype = gf100_fb_memtype_valid,
static const struct nvkm_fb_func
gf100_fb = {
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gf100_ram_new,
}.base;
.memtype_valid = gf100_fb_memtype_valid,
};
int
gf100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return gf100_fb_new_(&gf100_fb, device, index, pfb);
}

12
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
View File

@ -1,5 +1,6 @@
#ifndef __NVKM_RAM_NVC0_H__
#define __NVKM_RAM_NVC0_H__
#define gf100_fb(p) container_of((p), struct gf100_fb, base)
#include "priv.h"
struct gf100_fb {
@ -8,10 +9,9 @@ struct gf100_fb {
dma_addr_t r100c10;
};
int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void gf100_fb_dtor(struct nvkm_object *);
int gf100_fb_init(struct nvkm_object *);
bool gf100_fb_memtype_valid(struct nvkm_fb *, u32);
int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *,
int index, struct nvkm_fb **);
void *gf100_fb_dtor(struct nvkm_fb *);
void gf100_fb_init(struct nvkm_fb *);
void gf100_fb_intr(struct nvkm_fb *);
#endif

24
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c
View File

@ -24,15 +24,17 @@
#include "gf100.h"
#include "ram.h"
struct nvkm_oclass *
gk104_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xe0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_fb_ctor,
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.fini = _nvkm_fb_fini,
},
.memtype = gf100_fb_memtype_valid,
static const struct nvkm_fb_func
gk104_fb = {
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gk104_ram_new,
}.base;
.memtype_valid = gf100_fb_memtype_valid,
};
int
gk104_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return gf100_fb_new_(&gk104_fb, device, index, pfb);
}

48
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
View File

@ -19,47 +19,23 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "priv.h"
static int
gk20a_fb_init(struct nvkm_object *object)
static void
gk20a_fb_init(struct nvkm_fb *fb)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_device *device = fb->subdev.device;
int ret;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
return 0;
}
static int
gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
static const struct nvkm_fb_func
gk20a_fb = {
.init = gk20a_fb_init,
.memtype_valid = gf100_fb_memtype_valid,
};
int
gk20a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
struct nvkm_fb *fb;
int ret;
ret = nvkm_fb_create(parent, engine, oclass, &fb);
*pobject = nv_object(fb);
if (ret)
return ret;
return 0;
return nvkm_fb_new_(&gk20a_fb, device, index, pfb);
}
struct nvkm_oclass *
gk20a_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0xea),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = gk20a_fb_init,
.fini = _nvkm_fb_fini,
},
.memtype = gf100_fb_memtype_valid,
}.base;

24
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c
View File

@ -24,15 +24,17 @@
#include "gf100.h"
#include "ram.h"
struct nvkm_oclass *
gm107_fb_oclass = &(struct nvkm_fb_impl) {
.base.handle = NV_SUBDEV(FB, 0x07),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_fb_ctor,
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.fini = _nvkm_fb_fini,
},
.memtype = gf100_fb_memtype_valid,
static const struct nvkm_fb_func
gm107_fb = {
.dtor = gf100_fb_dtor,
.init = gf100_fb_init,
.intr = gf100_fb_intr,
.ram_new = gm107_ram_new,
}.base;
.memtype_valid = gf100_fb_memtype_valid,
};
int
gm107_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return gf100_fb_new_(&gm107_fb, device, index, pfb);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c
View File

@ -24,16 +24,14 @@
#include "nv50.h"
#include "ram.h"
struct nvkm_oclass *
gt215_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xa3),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram_new = gt215_ram_new,
static const struct nv50_fb_func
gt215_fb = {
.ram_new = gt215_ram_new,
.trap = 0x000d0fff,
}.base.base;
};
int
gt215_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nv50_fb_new_(&gt215_fb, device, index, pfb);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c
View File

@ -24,16 +24,14 @@
#include "nv50.h"
#include "ram.h"
struct nvkm_oclass *
mcp77_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaa),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram_new = mcp77_ram_new,
static const struct nv50_fb_func
mcp77_fb = {
.ram_new = mcp77_ram_new,
.trap = 0x001d07ff,
}.base.base;
};
int
mcp77_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nv50_fb_new_(&mcp77_fb, device, index, pfb);
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c
View File

@ -24,16 +24,14 @@
#include "nv50.h"
#include "ram.h"
struct nvkm_oclass *
mcp89_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0xaf),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram_new = mcp77_ram_new,
static const struct nv50_fb_func
mcp89_fb = {
.ram_new = mcp77_ram_new,
.trap = 0x089d1fff,
}.base.base;
};
int
mcp89_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nv50_fb_new_(&mcp89_fb, device, index, pfb);
}

54
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c
View File

@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
#include "regsnv04.h"
@ -30,60 +30,30 @@ nv04_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags)
{
if (!(tile_flags & 0xff00))
return true;
return false;
}
static int
nv04_fb_init(struct nvkm_object *object)
static void
nv04_fb_init(struct nvkm_fb *fb)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_device *device = fb->subdev.device;
int ret;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
* nvidia reading PFB_CFG_0, then writing back its original value.
* (which was 0x701114 in this case)
*/
nvkm_wr32(device, NV04_PFB_CFG0, 0x1114);
return 0;
}
static const struct nvkm_fb_func
nv04_fb = {
.init = nv04_fb_init,
.ram_new = nv04_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
struct nv04_fb_impl *impl = (void *)oclass;
struct nvkm_fb *fb;
int ret;
ret = nvkm_fb_create(parent, engine, oclass, &fb);
*pobject = nv_object(fb);
if (ret)
return ret;
fb->tile.regions = impl->tile.regions;
fb->tile.init = impl->tile.init;
fb->tile.comp = impl->tile.comp;
fb->tile.fini = impl->tile.fini;
fb->tile.prog = impl->tile.prog;
return 0;
return nvkm_fb_new_(&nv04_fb, device, index, pfb);
}
struct nvkm_oclass *
nv04_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x04),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv04_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv04_ram_new,
}.base.base;

49
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h
View File

@ -1,49 +0,0 @@
#ifndef __NVKM_FB_NV04_H__
#define __NVKM_FB_NV04_H__
#include "priv.h"
int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
struct nv04_fb_impl {
struct nvkm_fb_impl base;
struct {
int regions;
void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
void (*fini)(struct nvkm_fb *, int i,
struct nvkm_fb_tile *);
void (*prog)(struct nvkm_fb *, int i,
struct nvkm_fb_tile *);
} tile;
};
void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
int nv30_fb_init(struct nvkm_object *);
void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
int nv41_fb_init(struct nvkm_object *);
void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
int nv44_fb_init(struct nvkm_object *);
void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
#endif

25
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -54,19 +54,18 @@ nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
nvkm_rd32(device, 0x100240 + (i * 0x10));
}
struct nvkm_oclass *
nv10_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x10),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = _nvkm_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv10_ram_new,
static const struct nvkm_fb_func
nv10_fb = {
.tile.regions = 8,
.tile.init = nv10_fb_tile_init,
.tile.fini = nv10_fb_tile_fini,
.tile.prog = nv10_fb_tile_prog,
}.base.base;
.ram_new = nv10_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv10_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv10_fb, device, index, pfb);
}

25
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c
View File

@ -23,22 +23,21 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
struct nvkm_oclass *
nv1a_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x1a),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = _nvkm_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv1a_ram_new,
static const struct nvkm_fb_func
nv1a_fb = {
.tile.regions = 8,
.tile.init = nv10_fb_tile_init,
.tile.fini = nv10_fb_tile_fini,
.tile.prog = nv10_fb_tile_prog,
}.base.base;
.ram_new = nv1a_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv1a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv1a_fb, device, index, pfb);
}

27
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -34,7 +34,7 @@ nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
tile->limit = max(1u, addr + size) - 1;
tile->pitch = pitch;
if (flags & 4) {
fb->tile.comp(fb, i, size, flags, tile);
fb->func->tile.comp(fb, i, size, flags, tile);
tile->addr |= 2;
}
}
@ -77,20 +77,19 @@ nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp);
}
struct nvkm_oclass *
nv20_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x20),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = _nvkm_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv20_ram_new,
static const struct nvkm_fb_func
nv20_fb = {
.tile.regions = 8,
.tile.init = nv20_fb_tile_init,
.tile.comp = nv20_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv20_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv20_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv20_fb, device, index, pfb);
}

25
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
static void
@ -42,20 +42,19 @@ nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
}
}
struct nvkm_oclass *
nv25_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x25),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = _nvkm_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv20_ram_new,
static const struct nvkm_fb_func
nv25_fb = {
.tile.regions = 8,
.tile.init = nv20_fb_tile_init,
.tile.comp = nv25_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv20_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv25_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv25_fb, device, index, pfb);
}

47
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -34,8 +34,8 @@ nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
if (!(flags & 4)) {
tile->addr = (0 << 4);
} else {
if (fb->tile.comp) /* z compression */
fb->tile.comp(fb, i, size, flags, tile);
if (fb->func->tile.comp) /* z compression */
fb->func->tile.comp(fb, i, size, flags, tile);
tile->addr = (1 << 4);
}
@ -65,7 +65,7 @@ nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
static int
calc_bias(struct nvkm_fb *fb, int k, int i, int j)
{
struct nvkm_device *device = nv_device(fb);
struct nvkm_device *device = fb->subdev.device;
int b = (device->chipset > 0x30 ?
nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >>
(4 * (i ^ 1)) :
@ -88,16 +88,11 @@ calc_ref(struct nvkm_fb *fb, int l, int k, int i)
return x;
}
int
nv30_fb_init(struct nvkm_object *object)
void
nv30_fb_init(struct nvkm_fb *fb)
{
struct nvkm_device *device = nv_device(object);
struct nvkm_fb *fb = (void *)object;
int ret, i, j;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
struct nvkm_device *device = fb->subdev.device;
int i, j;
/* Init the memory timing regs at 0x10037c/0x1003ac */
if (device->chipset == 0x30 ||
@ -117,24 +112,22 @@ nv30_fb_init(struct nvkm_object *object)
calc_ref(fb, l, 1, j));
}
}
return 0;
}
struct nvkm_oclass *
nv30_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x30),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv20_ram_new,
static const struct nvkm_fb_func
nv30_fb = {
.init = nv30_fb_init,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv30_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv20_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv30_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv30_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
static void
@ -43,20 +43,20 @@ nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
}
}
struct nvkm_oclass *
nv35_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x35),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv20_ram_new,
static const struct nvkm_fb_func
nv35_fb = {
.init = nv30_fb_init,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv35_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv20_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv35_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv35_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
static void
@ -43,20 +43,20 @@ nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
}
}
struct nvkm_oclass *
nv36_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x36),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv30_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv20_ram_new,
static const struct nvkm_fb_func
nv36_fb = {
.init = nv30_fb_init,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv36_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv20_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv36_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv36_fb, device, index, pfb);
}

41
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -43,35 +43,26 @@ nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags,
}
}
static int
nv40_fb_init(struct nvkm_object *object)
static void
nv40_fb_init(struct nvkm_fb *fb)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_device *device = fb->subdev.device;
int ret;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
nvkm_mask(device, 0x10033c, 0x00008000, 0x00000000);
return 0;
nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000);
}
struct nvkm_oclass *
nv40_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x40),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv40_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv40_ram_new,
static const struct nvkm_fb_func
nv40_fb = {
.init = nv40_fb_init,
.tile.regions = 8,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv20_fb_tile_prog,
}.base.base;
.ram_new = nv40_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv40_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv40_fb, device, index, pfb);
}

41
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -37,35 +37,26 @@ nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp);
}
int
nv41_fb_init(struct nvkm_object *object)
void
nv41_fb_init(struct nvkm_fb *fb)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_device *device = fb->subdev.device;
int ret;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
nvkm_wr32(device, 0x100800, 0x00000001);
return 0;
nvkm_wr32(fb->subdev.device, 0x100800, 0x00000001);
}
struct nvkm_oclass *
nv41_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x41),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv41_ram_new,
static const struct nvkm_fb_func
nv41_fb = {
.init = nv41_fb_init,
.tile.regions = 12,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;
.ram_new = nv41_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv41_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv41_fb, device, index, pfb);
}

38
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
static void
@ -46,35 +46,27 @@ nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
nvkm_rd32(device, 0x100600 + (i * 0x10));
}
int
nv44_fb_init(struct nvkm_object *object)
void
nv44_fb_init(struct nvkm_fb *fb)
{
struct nvkm_fb *fb = (void *)object;
struct nvkm_device *device = fb->subdev.device;
int ret;
ret = nvkm_fb_init(fb);
if (ret)
return ret;
nvkm_wr32(device, 0x100850, 0x80000000);
nvkm_wr32(device, 0x100800, 0x00000001);
return 0;
}
struct nvkm_oclass *
nv44_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x44),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv44_ram_new,
static const struct nvkm_fb_func
nv44_fb = {
.init = nv44_fb_init,
.tile.regions = 12,
.tile.init = nv44_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;
.ram_new = nv44_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv44_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv44_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c
View File

@ -23,7 +23,7 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
void
@ -40,19 +40,19 @@ nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
tile->pitch = pitch;
}
struct nvkm_oclass *
nv46_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x46),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv44_ram_new,
static const struct nvkm_fb_func
nv46_fb = {
.init = nv44_fb_init,
.tile.regions = 15,
.tile.init = nv46_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;
.ram_new = nv44_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv46_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv46_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c
View File

@ -23,23 +23,23 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
struct nvkm_oclass *
nv47_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x47),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv41_ram_new,
static const struct nvkm_fb_func
nv47_fb = {
.init = nv41_fb_init,
.tile.regions = 15,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;
.ram_new = nv41_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv47_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv47_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c
View File

@ -23,23 +23,23 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
struct nvkm_oclass *
nv49_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x49),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv41_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv49_ram_new,
static const struct nvkm_fb_func
nv49_fb = {
.init = nv41_fb_init,
.tile.regions = 15,
.tile.init = nv30_fb_tile_init,
.tile.comp = nv40_fb_tile_comp,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv41_fb_tile_prog,
}.base.base;
.ram_new = nv49_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv49_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv49_fb, device, index, pfb);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c
View File

@ -23,22 +23,22 @@
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "nv04.h"
#include "priv.h"
#include "ram.h"
struct nvkm_oclass *
nv4e_fb_oclass = &(struct nv04_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x4e),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fb_ctor,
.dtor = _nvkm_fb_dtor,
.init = nv44_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv04_fb_memtype_valid,
.base.ram_new = nv4e_ram_new,
static const struct nvkm_fb_func
nv4e_fb = {
.init = nv44_fb_init,
.tile.regions = 12,
.tile.init = nv46_fb_tile_init,
.tile.fini = nv20_fb_tile_fini,
.tile.prog = nv44_fb_tile_prog,
}.base.base;
.ram_new = nv44_ram_new,
.memtype_valid = nv04_fb_memtype_valid,
};
int
nv4e_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
return nvkm_fb_new_(&nv4e_fb, device, index, pfb);
}

133
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
View File

@ -40,7 +40,14 @@ nv50_fb_memtype[0x80] = {
1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
};
bool
static int
nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram)
{
struct nv50_fb *fb = nv50_fb(base);
return fb->func->ram_new(&fb->base, pram);
}
static bool
nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype)
{
return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
@ -143,10 +150,11 @@ static const struct nvkm_enum vm_fault[] = {
};
static void
nv50_fb_intr(struct nvkm_subdev *subdev)
nv50_fb_intr(struct nvkm_fb *base)
{
struct nv50_fb *fb = (void *)subdev;
struct nvkm_device *device = fb->base.subdev.device;
struct nv50_fb *fb = nv50_fb(base);
struct nvkm_subdev *subdev = &fb->base.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_fifo *fifo = device->fifo;
struct nvkm_fifo_chan *chan;
const struct nvkm_enum *en, *re, *cl, *sc;
@ -202,19 +210,58 @@ nv50_fb_intr(struct nvkm_subdev *subdev)
nvkm_fifo_chan_put(fifo, flags, &chan);
}
int
nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
static void
nv50_fb_init(struct nvkm_fb *base)
{
struct nvkm_device *device = nv_device(parent);
struct nv50_fb *fb;
int ret;
struct nv50_fb *fb = nv50_fb(base);
struct nvkm_device *device = fb->base.subdev.device;
ret = nvkm_fb_create(parent, engine, oclass, &fb);
*pobject = nv_object(fb);
if (ret)
return ret;
/* Not a clue what this is exactly. Without pointing it at a
* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
* cause IOMMU "read from address 0" errors (rh#561267)
*/
nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);
/* This is needed to get meaningful information from 100c90
* on traps. No idea what these values mean exactly. */
nvkm_wr32(device, 0x100c90, fb->func->trap);
}
static void *
nv50_fb_dtor(struct nvkm_fb *base)
{
struct nv50_fb *fb = nv50_fb(base);
struct nvkm_device *device = fb->base.subdev.device;
if (fb->r100c08_page) {
dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE,
DMA_BIDIRECTIONAL);
__free_page(fb->r100c08_page);
}
return fb;
}
static const struct nvkm_fb_func
nv50_fb_ = {
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.intr = nv50_fb_intr,
.ram_new = nv50_fb_ram_new,
.memtype_valid = nv50_fb_memtype_valid,
};
int
nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device,
int index, struct nvkm_fb **pfb)
{
struct nv50_fb *fb;
if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
return -ENOMEM;
nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base);
fb->func = func;
*pfb = &fb->base;
fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
if (fb->r100c08_page) {
@ -227,59 +274,17 @@ nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_warn(&fb->base.subdev, "failed 100c08 page alloc\n");
}
nv_subdev(fb)->intr = nv50_fb_intr;
return 0;
}
void
nv50_fb_dtor(struct nvkm_object *object)
{
struct nvkm_device *device = nv_device(object);
struct nv50_fb *fb = (void *)object;
if (fb->r100c08_page) {
dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE,
DMA_BIDIRECTIONAL);
__free_page(fb->r100c08_page);
}
nvkm_fb_destroy(&fb->base);
}
static const struct nv50_fb_func
nv50_fb = {
.ram_new = nv50_ram_new,
.trap = 0x000707ff,
};
int
nv50_fb_init(struct nvkm_object *object)
nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
struct nv50_fb_impl *impl = (void *)object->oclass;
struct nv50_fb *fb = (void *)object;
struct nvkm_device *device = fb->base.subdev.device;
int ret;
ret = nvkm_fb_init(&fb->base);
if (ret)
return ret;
/* Not a clue what this is exactly. Without pointing it at a
* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
* cause IOMMU "read from address 0" errors (rh#561267)
*/
nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);
/* This is needed to get meaningful information from 100c90
* on traps. No idea what these values mean exactly. */
nvkm_wr32(device, 0x100c90, impl->trap);
return 0;
return nv50_fb_new_(&nv50_fb, device, index, pfb);
}
struct nvkm_oclass *
nv50_fb_oclass = &(struct nv50_fb_impl) {
.base.base.handle = NV_SUBDEV(FB, 0x50),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_fb_ctor,
.dtor = nv50_fb_dtor,
.init = nv50_fb_init,
.fini = _nvkm_fb_fini,
},
.base.memtype = nv50_fb_memtype_valid,
.base.ram_new = nv50_ram_new,
.trap = 0x000707ff,
}.base.base;

14
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
View File

@ -1,23 +1,21 @@
#ifndef __NVKM_FB_NV50_H__
#define __NVKM_FB_NV50_H__
#define nv50_fb(p) container_of((p), struct nv50_fb, base)
#include "priv.h"
struct nv50_fb {
const struct nv50_fb_func *func;
struct nvkm_fb base;
struct page *r100c08_page;
dma_addr_t r100c08;
};
int nv50_fb_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void nv50_fb_dtor(struct nvkm_object *);
int nv50_fb_init(struct nvkm_object *);
struct nv50_fb_impl {
struct nvkm_fb_impl base;
struct nv50_fb_func {
int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **);
u32 trap;
};
int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, int index,
struct nvkm_fb **pfb);
extern int nv50_fb_memtype[0x80];
#endif

75
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
View File

@ -1,37 +1,62 @@
#ifndef __NVKM_FB_PRIV_H__
#define __NVKM_FB_PRIV_H__
#define nvkm_fb(p) container_of((p), struct nvkm_fb, subdev)
#include <subdev/fb.h>
struct nvkm_bios;
#define nvkm_fb_create(p,e,c,d) \
nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d)
#define nvkm_fb_destroy(p) ({ \
struct nvkm_fb *_fb = (p); \
_nvkm_fb_dtor(nv_object(_fb)); \
})
#define nvkm_fb_init(p) ({ \
struct nvkm_fb *_fb = (p); \
_nvkm_fb_init(nv_object(_fb)); \
})
#define nvkm_fb_fini(p,s) ({ \
struct nvkm_fb *_fb = (p); \
_nvkm_fb_fini(nv_object(_fb), (s)); \
})
struct nvkm_fb_func {
void *(*dtor)(struct nvkm_fb *);
void (*init)(struct nvkm_fb *);
void (*intr)(struct nvkm_fb *);
int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
void _nvkm_fb_dtor(struct nvkm_object *);
int _nvkm_fb_init(struct nvkm_object *);
int _nvkm_fb_fini(struct nvkm_object *, bool);
struct {
int regions;
void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
} tile;
struct nvkm_fb_impl {
struct nvkm_oclass base;
int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **);
bool (*memtype)(struct nvkm_fb *, u32);
bool (*memtype_valid)(struct nvkm_fb *, u32 memtype);
};
bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
bool nv50_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
void nvkm_fb_ctor(const struct nvkm_fb_func *, struct nvkm_device *device,
int index, struct nvkm_fb *);
int nvkm_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *device,
int index, struct nvkm_fb **);
int nvkm_fb_bios_memtype(struct nvkm_bios *);
int nvkm_fb_bios_memtype(struct nvkm_bios *);
bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype);
void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *);
void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv30_fb_init(struct nvkm_fb *);
void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags,
struct nvkm_fb_tile *);
void nv41_fb_init(struct nvkm_fb *);
void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv44_fb_init(struct nvkm_fb *);
void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *);
void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size,
u32 pitch, u32 flags, struct nvkm_fb_tile *);
bool gf100_fb_memtype_valid(struct nvkm_fb *, u32);
#endif

9
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
View File

@ -57,10 +57,7 @@ ramfuc_reg(u32 addr)
static inline int
ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb)
{
struct nvkm_pmu *pmu = nvkm_pmu(fb);
int ret;
ret = nvkm_memx_init(pmu, &ram->memx);
int ret = nvkm_memx_init(fb->subdev.device->pmu, &ram->memx);
if (ret)
return ret;
@ -148,9 +145,7 @@ ramfuc_train(struct ramfuc *ram)
static inline int
ramfuc_train_result(struct nvkm_fb *fb, u32 *result, u32 rsize)
{
struct nvkm_pmu *pmu = nvkm_pmu(fb);
return nvkm_memx_train_result(pmu, result, rsize);
return nvkm_memx_train_result(fb->subdev.device->pmu, result, rsize);
}
static inline void

2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
View File

@ -1457,7 +1457,7 @@ gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
struct dcb_gpio_func func;
struct gk104_ram *ram;
int ret, i;
u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb));
u8 ramcfg = nvbios_ramcfg_index(subdev);
u32 tmp;
if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))

5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View File

@ -77,14 +77,15 @@ static void
nv50_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt,
struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
struct nvkm_ram *ram = vma->vm->mmu->subdev.device->fb->ram;
u32 comp = (mem->memtype & 0x180) >> 7;
u32 block, target;
int i;
/* IGPs don't have real VRAM, re-target to stolen system memory */
target = 0;
if (nvkm_fb(vma->vm->mmu)->ram->stolen) {
phys += nvkm_fb(vma->vm->mmu)->ram->stolen;
if (ram->stolen) {
phys += ram->stolen;
target = 3;
}